Semiconductor device having semiconductor regions of different conductivity types provided at a predetermined interval along a first direction

Patent metadata

Field	Value
Publication number	US-10847641-B2
Application number	US-201816171680-A
Country	US
Kind code	B2
Filing date	Oct 26, 2018
Priority date	Nov 17, 2016
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

Among trenches disposed in a striped-shape parallel to a front surface of a semiconductor substrate, a gate electrode at a gate potential is provided in a gate trench, via a gate insulating film; and in a dummy trench, a dummy gate electrode at an emitter electric potential is provided, via a dummy gate insulating film. Among mesa regions, in a first mesa region functioning as a MOS gate, a first p-type base region is provided in a surface region overall. In a second mesa region not functioning as a MOS gate, a second p-type base region is selectively provided at a predetermined interval, along a first direction. At least one of the trenches on each side of a mesa region is a gate trench and at at least one side wall of the gate trench, a MOS gate is driven. As a result, the ON voltage may be reduced.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of trenches reaching a predetermined depth from a front surface of a semiconductor substrate of a first conductivity type, the plurality of trenches being disposed in a striped layout along a first direction parallel to the front surface of the semiconductor substrate;
a plurality of gate electrodes provided in the plurality of trenches, via a plurality of gate insulating films;
a first gate electrode of the plurality of gate electrodes and contributing to element control;
a second gate electrode of the plurality of the gate electrodes other than the first gate electrode;
a first trench of the plurality of trenches and in which the first gate electrode is provided;
a second trench of the plurality of trenches and in which the second gate electrode is provided;
a plurality of mesa regions between adjacent trenches of the plurality of trenches;
a first semiconductor region of a second conductivity type provided in a first mesa region of the plurality of mesa regions, extending in the first direction along an entire length of an active region of the semiconductor substrate, at a depth shallower from the front surface of the semiconductor substrate than is the plurality of trenches;
a second semiconductor region of the second conductivity type provided in a second mesa region of the plurality of mesa regions other than the first mesa region, the second semiconductor region being provided at a depth shallower from the front surface of the semiconductor substrate than is the plurality of trenches, at a predetermined interval along the first direction;
a third semiconductor region of the first conductivity type provided in the first semiconductor region at a predetermined interval along the first direction;
a fourth semiconductor region of the second conductivity type provided at a rear surface of the semiconductor substrate;
a first electrode electrically connected with the first semiconductor region, the second semiconductor region, the third semiconductor region and the second gate electrode; and
a second electrode electrically connected with the fourth semiconductor region, wherein
the first trench is at least one of the adjacent trenches on each side of the first mesa region, and
the second trench is at least one of the adjacent trenches on each side of the second mesa region.

2. The semiconductor device according to claim 1 , wherein
the second mesa region opposes an adjacent second mesa region, across the first trench in a second direction orthogonal to the first direction.

3. The semiconductor device according to claim 1 , wherein
the second mesa region opposes an adjacent second mesa region, across the second trench in a second direction orthogonal to the first direction.

4. The semiconductor device according to claim 1 , wherein
the first mesa region is sandwiched by the first trench and an adjacent first trench.

5. The semiconductor device according to claim 1 , further comprising
a fifth semiconductor region of the first conductivity type provided in the first mesa region overall, at a position deeper from the front surface of the semiconductor substrate than is the first semiconductor region, the fifth semiconductor region being in contact with the first semiconductor region and having an impurity concentration higher than that of the semiconductor substrate.

6. The semiconductor device according to claim 5 , wherein
the fifth semiconductor region is further provided in the second mesa region overall, at a position deeper from the front surface of the semiconductor substrate than is the second semiconductor region, the fifth semiconductor region being in contact with the second semiconductor region.

7. The semiconductor device according to claim 5 , wherein
the fifth semiconductor region is further provided in a region opposing the second semiconductor region in a depth direction, the fifth semiconductor region being provided at a position deeper from the front surface of the semiconductor substrate than is the second semiconductor region and provided being in contact with the second semiconductor region.

8. The semiconductor device according to claim 1 , further comprising:
a third trench of the plurality of trenches and in which the second gate electrode is provided;
a third mesa region of the plurality of mesa regions and between the adjacent trenches that include at least the third trench;
a sixth semiconductor region of the second conductivity type provided in the third mesa region overall, at a depth shallower from the front surface of the semiconductor substrate than is the plurality of trenches;
a seventh semiconductor region of the first conductivity type provided adjacent to the fourth semiconductor region along a direction parallel to the rear surface of the semiconductor substrate, the seventh semiconductor region being in contact with the fourth semiconductor region and opposing the sixth semiconductor region in a depth direction, the seventh semiconductor region having an impurity concentration higher than that of the semiconductor substrate;
a first element region in which the first trench and the second trench are disposed;
a second element region in which the third trench is disposed;
two fourth trenches of the plurality of trenches and in which the second gate electrode is provided, the two fourth trenches being disposed in a boundary region of the first element region and the second element region;
a fourth mesa region of the plurality of mesa regions and sandwiched by the two fourth trenches;
an eighth semiconductor region of the second conductivity type provided in the fourth mesa region overall, at a depth shallower from the front surface of the semiconductor substrate than is the plurality of trenches; and
a ninth semiconductor region of the second conductivity type provided in the eighth semiconductor region overall, at a depth shallower from the front surface of the semiconductor substrate than is the eighth semiconductor region, the ninth semiconductor region having an impurity concentration higher than that of the eighth semiconductor region, wherein
the sixth semiconductor region and the ninth semiconductor region are electrically connected with the first electrode,
the seventh semiconductor region is electrically connected with the second electrode,
of the two fourth trenches, a fourth trench nearest the first element region is adjacent to the first trench, and the second mesa region is disposed between the fourth trench nearest the first element region and the first trench adjacent thereto, and
of the two fourth trenches, a fourth trench nearest the second element region is adjacent to the third trench, and the third mesa region is disposed between the fourth trench nearest the second element region and the third trench adjacent thereto.

9. The semiconductor device according to claim 8 , wherein
a boundary of the fourth semiconductor region and the seventh semiconductor region opposes in the depth direction, the fourth trench nearest the second element region of the two fourth trenches.

10. The semiconductor device according to claim 8 , wherein
a distance from the boundary of the fourth semiconductor region and the seventh semiconductor region, to the third semiconductor region disposed nearest the boundary region is at least a sum of a width of the eighth semiconductor region, a width of the second mesa region in the first element region and nearest the second element region, and widths of the adjacent trenches on each side of the second mesa region.

11. The semiconductor device according to claim 1 , further comprising:
a fifth semiconduc

Assignees

• Fuji Electric Co Ltd

Inventors

• Abe Hitoshi
• Fujii Takeshi
• Obata Tomoyuki

Classifications

• H10D64/232

  Emitter electrodes for IGBTs · CPC title

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title