Display panel

Patent metadata

Field	Value
Publication number	US-10847599-B2
Application number	US-201916382308-A
Country	US
Kind code	B2
Filing date	Apr 12, 2019
Priority date	Sep 21, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A display panel including a substrate including a transmissive area, a first non-display area surrounding the transmissive area, and a display area that at least partially surrounds the first non-display area; a display element in the display area and including a pixel electrode; a plurality of scan lines extending from the display area, arranged in the first non-display area, and detouring along an edge of the transmissive area; a connection line in the first non-display area, at least partially overlapping the plurality of scan lines, and on a same layer as that of the pixel electrode; and a first line and a second line on a layer different from that of the connection line, wherein the first line and the second line are connected to the connection line through contact holes.

First claim

What is claimed is:

1. A display panel, comprising:
a substrate including a transmissive area, a first non-display area surrounding the transmissive area, and a display area that at least partially surrounds the first non-display area;
a display element in the display area and including a pixel electrode;
a plurality of scan lines extending from the display area, arranged in the first non-display area, and detouring along an edge of the transmissive area;
a connection line in the first non-display area, at least partially overlapping the plurality of scan lines, and on a same layer as that of the pixel electrode; and
a first line and a second line on a layer different from that of the connection line,
wherein the first line and the second line are connected to the connection line through contact holes.

2. The display panel as claimed in claim 1 , wherein:
the plurality of scan lines each extend in a first direction and include a curved portion in the first non-display area, and
the connection line extends in the first direction and includes a straight line portion in the first non-display area.

3. The display panel as claimed in claim 1 , wherein the connection line is on a planarization layer having a flat top surface.

4. The display panel as claimed in claim 1 , further comprising a plurality of electrode voltage lines adjacent to the plurality of scan lines with an insulating layer therebetween and detouring along an edge of the transmissive area.

5. The display panel as claimed in claim 4 , wherein the plurality of scan lines does not overlap the plurality of electrode voltage lines.

6. The display panel as claimed in claim 4 , further comprising:
a driving thin film transistor in the display area, the driving thin film transistor including a driving gate electrode; and
a storage capacitor in the display area, the storage capacitor overlapping the driving thin film transistor,
wherein:
the plurality of scan lines are on the same layer as that of the driving gate electrode, and
the plurality of electrode voltage lines are on the same layer as that of a second storage capacitor plate of the storage capacitor.

7. The display panel as claimed in claim 1 , further comprising a first scan circuit and a second scan circuit in a second non-display area surrounding the display area and the first non-display area, the first scan circuit and the second scan circuit being configured to provide a scan signal,
wherein:
the transmissive area is partially surrounded by the display area,
the first line is connected to the first scan circuit and extends along the second non-display area, and
the second line is connected to the second scan circuit and extends along the second non-display area.

8. The display panel as claimed in claim 7 , further comprising a common power voltage wiring in the second non-display area, the common power voltage wiring surrounding at least a portion of the display area and being configured to transfer a common voltage to the display area,
wherein the connection line is between the transmissive area and the common power voltage wiring.

9. The display panel as claimed in claim 7 , further comprising an electrode layer in the first non-display area, the electrode layer being on the same layer as that of the connection line and having an open ring shape.

10. The display panel as claimed in claim 1 , wherein:
the first non-display area is entirely surrounded by the display area, and
the first line and the second line extend from the display area.

11. The display panel as claimed in claim 10 , wherein:
the connection line extends in a first direction and the first line, and
the second line extends in a second direction intersecting with the first direction.

12. A display panel, comprising:
a substrate including a transmissive area, a display area partially surrounding the transmissive area, and a non-display area outside the display area;
a display element in the display area and including a pixel electrode;
a first scan driving circuit and a second scan driving circuit in the non-display area with the display area therebetween;
a first driving wiring extending from the first scan driving circuit;
a second driving wiring extending from the second scan driving circuit; and
a connection line connected to the first driving wiring and the second driving wiring through contact holes and being on the same layer as that of the pixel electrode,
wherein the connection line is in the non-display area on one side of the transmissive area.

13. The display panel as claimed in claim 12 , wherein:
the first driving wiring and a second driving wiring extend in a first direction and include a curved portion around the transmissive area, and
the connection line extends in the first direction and includes a straight line portion overlapping with the curved portion.

14. The display panel as claimed in claim 12 , wherein the connection line is on a planarization layer having a flat top surface.

15. The display panel as claimed in claim 12 , further comprising a plurality of electrode voltage lines adjacent to the first driving wiring and a second driving wiring with an insulating layer therebetween and detouring around an edge of the transmissive area.

16. The display panel as claimed in claim 15 , further comprising:
an interlayer insulating layer covering the plurality of electrode voltage lines;
a data line on the interlayer insulating layer; and
a planarization layer covering the data line,
wherein:
the first driving wiring and the second driving wiring are on the interlayer insulating layer,
the connection line is on the planarization layer, and
a thickness of the planarization layer is greater than a thickness of the interlayer insulating layer.

17. The display panel as claimed in claim 15 , further comprising:
a driving thin film transistor in the display area, the driving thin film transistor including a driving gate electrode; and
a storage capacitor in the display area, the storage capacitor overlapping the driving thin film transistor,
wherein:
the plurality of scan lines are on the same layer as that of the driving gate electrode, and
the plurality of electrode voltage lines are on the same layer as that of a second storage capacitor plate of the storage capacitor.

18. The display panel as claimed in claim 15 , wherein the plurality of scan lines do not overlap the plurality of electrode voltage lines.

19. The display panel as claimed in claim 12 , further comprising a common power voltage wiring in the non-display area, the common power voltage wiring surrounding at least a portion of the display area and being configured to transfer a common voltage to the display area,
wherein the connection line is between the transmissive area and the common power voltage wiring.

20. The display panel as claimed in claim 12 , further comprising an electrode layer around the transmissive area, the electrode layer being on the same layer as that of the connection line and having an open ring shape.

Assignees

• Samsung Display Co Ltd

Inventors

• Jeon Yujin
• Kim Daesuk
• Kim Sukyoung
• Sung Seungwoo
• Lee Wonse
• Cha Hyunji

Classifications

• H10K59/8731

  multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

• H10K59/871

  Self-supporting sealing arrangements · CPC title

• H10K50/88

  Terminals, e.g. bond pads · CPC title

• H10K59/351

  comprising more than three subpixels, e.g. red-green-blue-white [RGBW] · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title