Semiconductor devices, memory dies and related methods

Patent metadata

Field	Value
Publication number	US-10847518-B2
Application number	US-201715829420-A
Country	US
Kind code	B2
Filing date	Dec 1, 2017
Priority date	Jan 21, 2016
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A semiconductor substrate is provided. Active areas and trench isolation regions are formed. The active areas extend along a first direction. Buried word lines extending along a second direction are formed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. Buried digit lines extending along a third direction are formed above the buried word lines. An upper portion of the trench isolation region is removed to form an L-shaped recessed area around each of the cell contact areas. The L-shaped recessed area exposes sidewalls of the cell contact areas. An epitaxial silicon growth process is then performed to grow an epitaxial silicon layer from the exposed sidewalls and a top surface of each of the cell contact areas, thereby forming enlarged cell contact areas.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a material including active areas;
an isolation region;
buried word lines extending along the material, at least one of the buried word lines and the isolation region intersecting with at least one of the active areas, the at least one of the buried word lines and the isolation region separating the at least one of the active areas into at least two portions including at least one cell contact area and a digit line contact area;
buried digit lines extending along the material, at least one of the buried digit lines positioned adjacent to the digit line contact area;
a cap material over the buried digit lines;
an epitaxial silicon material adjacent to the at least one cell contact area, wherein the epitaxial silicon material has a top surface higher than a top surface of the cap material and a bottom surface at the same height as the top surface of the cap material; and
dielectric material over the epitaxial silicon material, the dielectric material being in contact with the top surface of the cap material and the top surface of the epitaxial silicon material.

2. The semiconductor device of claim 1 , wherein the isolation region comprises isolation regions positioned between each of the active areas.

3. The semiconductor device of claim 1 , wherein the at least one of the buried word lines and the isolation region separates the at least one of the active areas into three portions.

4. The semiconductor device of claim 3 , wherein the three portions of the at least one of the active areas comprises two cell contact areas and the digit line contact area.

5. The semiconductor device of claim 1 , wherein each of the buried word lines intersects with at least one of the active areas.

6. The semiconductor device of claim 1 , wherein the active areas extend along a first direction and the buried word lines extend along a second direction transverse to the first direction.

7. The semiconductor device of claim 6 , wherein the buried digit lines extend along a third direction transverse to the second direction.

8. The semiconductor device of claim 1 , wherein the top surface of the buried digit lines is flush with a top surface of the at least one cell contact area.

9. The semiconductor device of claim 1 , wherein the epitaxial silicon material extends from at least one exposed sidewall and a top surface of the at least one cell contact area.

10. A memory die, comprising:
a material including active areas;
word lines extending along the material, the word lines intersecting with at least one of the active areas, at least one of the word lines separating the at least one of the active areas into at least two portions including at least one cell contact area and a digit line contact area;
digit lines extending along the material, at least one of the digit lines positioned adjacent to the digit line contact area;
a cap material extending along the digit lines; and
a silicon material adjacent to the at least one cell contact area, wherein the silicon material has a top surface higher than a top surface of the cap material, wherein the top surface of the cap material and a top surface of the active areas are both positioned at a same height from a bottom of the material, and wherein a bottom surface of the silicon material is positioned at the same height from the bottom of the material.

11. The memory die of claim 10 , wherein the digit lines intersect with the active areas at an acute angle.

12. The memory die of claim 10 , further comprising a capacitor directly on the silicon material.

13. The memory die of claim 10 , further comprising an isolation region separating the active areas.

14. The memory die of claim 13 , further comprising an open recessed volume between the digit line contact area and the silicon material.

15. The memory die of claim 14 , wherein the open recessed volume is directly over the isolation region.

16. A semiconductor device, comprising:
a material including active areas;
word lines extending along the material, the word lines intersecting with at least one of the active areas, at least one of the word lines separating the at least one of the active areas into at least two portions including at least one cell contact area and a digit line contact area;
digit lines extending along the material, at least one of the digit lines positioned adjacent to the digit line contact area;
a cap material extending along the digit lines; and
a silicon material adjacent to the at least one cell contact area, wherein the silicon material has a top surface higher than a top surface of one of the cap material and a bottom surface extending in a plane with the top surface of the one of the cap material.

17. The semiconductor device of claim 16 , wherein the top surface of the one of the digit lines is flush with a top surface of the at least one cell contact area.

18. The semiconductor device of claim 17 , wherein the silicon material extends from at least one exposed sidewall and the top surface of the at least one cell contact area.

Assignees

• Micron Technology Inc

Inventors

• Wang Kuo-Chen

Classifications

• H10D1/00 Primary

  Resistors, capacitors or inductors · CPC title

• H10B12/02 Primary

  for one transistor one-capacitor [1T-1C] memory cells · CPC title

• H01L27/10888 Primary

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic