Remapping operations

Patent metadata

Field	Value
Publication number	US-10847235-B2
Application number	US-201515761111-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A remapping rate of remapping operations on a memory module may be determined. Each remapping operation may comprise storing a pointer to an unfailed memory location within a failed memory location. A wear-leveling rate on the memory module may be adjusted based on the remapping rate.

First claim

The invention claimed is:

1. A method, comprising:
determining a remapping rate of remapping operations on a memory module, each remapping operation comprising storing a pointer to an unfailed memory location within a failed memory location; and
adjusting a wear-leveling rate on the memory module based on the remapping rate, including:
increasing the wear-leveling rate if the remappinq rate exceeds a remapping rate threshold value; and
decreasing the wear-leveling rate if the remappinq rate is below a second remappinq rate threshold value.

2. The method of claim 1 , wherein determining the rate of remapping operations comprising:
maintaining a counter of remapping operations; and
reading the counter at a counter reading rate.

3. The method of claim 1 , further comprising:
reducing a functionality of the memory module if the remapping rate exceeds a second remapping rate threshold value.

4. The method of claim 3 , wherein reducing the functionality of the memory module comprises reducing write access to the failed memory location or reducing a bandwidth of the memory module.

5. The method of claim 1 , further comprising:
sending an alert based on the remapping rate.

6. A memory system, comprising:
a memory device comprising a plurality of memory locations;
a memory control unit to remap a failed memory location to an unfailed memory location by storing a pointer to the unfailed memory location in the failed memory location; and
a counter to maintain a count of remapping operations wherein the memory control unit is to:
perform wear-leveling on the memory device at a wear-leveling rate;
use the counter to determine a remapping rate, and modify the wear-leveling rate based on the remapping rate by increasing the wear-leveling rate if the remapping rate exceeds a first threshold and decreasing the wear-leveling rate if the remapping rate is lower than a second threshold.

7. The memory system of claim 6 , wherein the memory control unit is to:
use the counter to determine a remapping rate; and
send an alert if the remapping rate exceeds a threshold.

8. A system, comprising:
a processor;
a memory module;
a remapper to remap a failed memory location of the memory module to an unfailed memory location of the memory module by storing a pointer to the unfailed memory location;
a rate determiner to determine a remapping rate; and
a wear leveler to perform memory wear-leveling at a wear level rate set according to the remapping rate; and
a memory control unit comprising the rate determiner, wherein the memory control unit is to reduce a functionality of the memory module if the remapping rate exceeds a threshold.

9. The system of claim 8 , wherein:
the rate determiner is to provide an alert and address of the failed memory location if the remapping rate exceeds a threshold; and
the system further comprises a non-transitory computer readable medium storing instructions executable by the processor to:
use the address of the faded memory location to identify a process contributing to memory failure.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Akkerman Ryan
• Warner Craig
• Orth Joseph

Classifications

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/3495 Primary

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title