Hybrid memory module

Patent metadata

Field	Value
Publication number	US-10847196-B2
Application number	US-201716344321-A
Country	US
Kind code	B2
Filing date	Oct 10, 2017
Priority date	Oct 31, 2016
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

First claim

What is claimed is:

1. A memory module comprising:
a rank of dynamic random-access memory (DRAM) components, each of the DRAM components of a DRAM data width, the rank of DRAM components having a rank width of the sum of the DRAM data widths;
a nonvolatile memory component of a nonvolatile data width less than the rank width, the nonvolatile memory component storing nonvolatile cache lines; and
a module controller coupled to the DRAM components and the nonvolatile memory component, the module controller to distribute the nonvolatile cache lines from the nonvolatile memory component across the DRAM components, each DRAM component caching a subset of each distributed nonvolatile cache line.

2. The memory module of claim 1 , further comprising data-buffer components coupled to the DRAM components to communicate the subsets of each distributed nonvolatile cache line with the nonvolatile memory component.

3. The memory module of claim 2 , further comprising a module connector coupled to the data-buffer components, the module connector to communicate the subsets of each distributed nonvolatile cache line from the memory module.

4. The memory module of claim 1 , wherein the nonvolatile memory component is one of a number of nonvolatile memory components, the module further comprising a multi-drop data bus from the module controller to the nonvolatile memory components.

5. The memory module of claim 1 , further comprising a set of point-to-point links between the module controller and the DRAM components, the point-to-point links to convey the subsets of the distributed nonvolatile cache lines to the DRAM components.

6. The memory module of claim 1 , wherein the nonvolatile memory component stores the nonvolatile cache lines at corresponding nonvolatile cache-line addresses having nonvolatile-page bits, the module controller mapping the nonvolatile-page bits to select among the DRAM components.

7. The memory module of claim 6 , each DRAM component comprising DRAM dies, the nonvolatile-page bits to select among the DRAM dies.

8. The memory module of claim 1 , the rank of DRAM components caching the nonvolatile cache lines as DRAM cache lines, each DRAM cache line including cache tag bits.

9. The memory module of claim 8 , the DRAM components further caching the cache tag bits at a common DRAM address.

10. The memory module of claim 9 , wherein the common DRAM address comprises a DRAM cache-line address identifying a DRAM location distributed across the DRAM components.

11. The memory module of claim 9 , wherein the cache tag bits express first cache tags of a first cache associativity, the module controller maintaining second cache tags of a second associativity at the common DRAM address.

12. The memory module of claim 11 , wherein the first cache tags are direct-mapped cache tags.

13. The memory module of claim 12 , wherein the second cache tags are multi-set cache tags.

14. The memory module of claim 12 , wherein the first cache exhibits a first cache latency and the second cache exhibits a second cache latency greater than the first cache latency.

15. The memory module of claim 1 , the nonvolatile cache lines designated using nonvolatile cache-line addresses having nonvolatile-line bits and nonvolatile-device bits, the DRAM components collectively storing DRAM address lines designated using DRAM cache-line addresses having DRAM-line bits and DRAM-device bits; the module controller including address-mapping logic to map the nonvolatile-line bits to the DRAM-device bits.

16. The memory module of claim 15 , the address-mapping logic to map the DRAM-line bits to the nonvolatile-device bits.

17. The memory module of claim 1 , each of the nonvolatile cache lines designated using a set of nonvolatile-page bits, wherein the module controller includes address-mapping logic to map each external controller page address to any of the sets of nonvolatile-page bits.

18. The memory module of claim 1 , wherein the nonvolatile memory components comprise flash memory.

19. A method of writing to a cache memory having a direct cache and a multi-set cache, the method comprising:
receiving a write command directing write data to a nonvolatile-memory address;
reading from the cache memory a tag cache line of direct cache tags and multi-set cache tags;
determining, from the cache tag line, whether the nonvolatile address has a corresponding entry in the cache memory; and
if the data cache line is in the cache memory, writing the write data to the cache memory and updating the tag cache line.

20. The method of claim 19 , further comprising determining, from the cache tag line, whether the corresponding entry is in the direct cache.

21. The method of claim 19 , further comprising determining, from the cache tag line, whether the corresponding entry in the cache memory is dirty.

22. The method of claim 21 , further comprising writing the corresponding entry from the cache memory to a nonvolatile memory if the corresponding entry in the cache memory is dirty.

23. The method of claim 22 , wherein writing the corresponding entry from the cache memory to the nonvolatile memory comprising reading the corresponding entry in parallel from a rank of DRAM components and writing the corresponding entry into a single nonvolatile memory die.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Linstadt John Eric
• Wright Kenneth L

Classifications

• A45F2003/001

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• A45F3/04

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• A41D3/04

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• G11C2207/2245

  Memory devices with an internal cache buffer · CPC title

• G06F2212/1041

  Resource optimization · CPC title