Data copy to non-volatile memory

Patent metadata

Field	Value
Publication number	US-10846219-B2
Application number	US-201515748639-A
Country	US
Kind code	B2
Filing date	Jul 31, 2015
Priority date	Jul 31, 2015
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A system and method for a computing device having a processor, a memory module including volatile memory for random access memory (RAM), and an integrated circuit to intercept an error signal from the processor, the intercept delaying a system shutdown of the computing device. Firmware is executed by the processor to copy contents of the volatile memory to a non-volatile memory during the delay of the system shutdown.

First claim

What is claimed is:

1. A computing device comprising:
a processor to transmit a catastrophic error signal to a hub of the computing device responsive to the computing device experiencing an error or shutdown triggering event;
a memory module comprising volatile memory for random access memory (RAM);
the hub to shut down the computing device upon receipt of the catastrophic error signal;
an integrated circuit to intercept the catastrophic error signal upon transmission to the hub, the intercept delaying a system shutdown of the computing device; and
firmware executed by the processor to, responsive to the error signal intercept, copy contents of the volatile memory to a non-volatile memory,
wherein the integrated circuit delays the system shutdown of the computing device by a pulse where the error is recoverable or a hold where the error is non-recoverable.

2. The computing device of claim 1 , comprising the non-volatile memory.

3. The computing device of claim 1 , wherein the non-volatile memory is external to the memory module.

4. The computing device of claim 1 , wherein the memory module comprises a dual in-line memory module (DIMM).

5. The computing device of claim 1 , wherein the integrated circuit comprises a programmable logic device (PLD) or a complex programmable logic device (CPLD).

6. The computing device of claim 1 , wherein the hub is a south bridge or a platform controller hub (PCH).

7. The computing device of claim 1 , comprising:
a memory controller to facilitate the copy of the contents of the volatile memory to the non-volatile memory during the delay of the system shutdown; and
a power supply unit (PSU) to convert alternating current (AC) to direct current (DC), wherein the PSU further comprises an embedded uninterruptible power supply (UPS) to provide power for the copy of the contents of the volatile memory to the non-volatile memory during the delay of the system shutdown.

8. The computing device of claim 1 , wherein the integrated circuit generates an interrupt to pull the processor out of normal runtime Operating System operation into a basic input/output system (BIOS) controlled environment copy for copying the contents of the volatile memory to a non-volatile memory.

9. A method comprising:
responsive to a catastrophic error at a computing device, issuing a catastrophic error signal from a processor of the computing device to a hub to shutdown the computing device in response to receiving the catastrophic error, the computing device comprising a processor, firmware, an integrated circuit, and a memory module having volatile memory;
intercepting by the integrated circuit the catastrophic error signal upon transmission to the hub; and
responsive to intercepting the signal, copying, via the firmware, data from the volatile memory to non-volatile memory,
wherein the integrated circuit delays the system shutdown of the computing device by a pulse where the error is recoverable or a hold where the error is non-recoverable.

10. The method of claim 9 , wherein the non-volatile memory is external to the memory module.

11. The method of claim 9 , wherein the copying is via the firmware and a system memory controller, and wherein the error comprises a trigger event resulting in a system shutdown of the computing device.

12. A tangible, non-transitory, computer-readable medium comprising instructions that direct a processor to:
intercept a catastrophic error signal transmitted from a processor intended for a hub architecture of a computing device to shutdown the computing device, the intercept to delay the shutdown of the computing device; and
responsive to the error signal intercept, copy, via firmware of the computing device, data from volatile memory of a memory module of the computing device to non-volatile memory,
wherein the integrated circuit delays the system shutdown of the computing device by a pulse where the error is recoverable or a hold where the error is non-recoverable.

13. The computer-readable medium of claim 12 , wherein the copying of data from the volatile memory to the non-volatile memory is self-contained on the memory module.

14. The computer-readable medium of claim 12 , wherein the non-volatile memory is external to the memory module.

15. A memory module comprising:
volatile memory for Random Access Memory (RAM);
an integrated circuit to intercept a catastrophic error signal from a processor to a hub of a computing device, the hub to shut down the computing device upon receipt of the catastrophic error such that an intercept of the catastrophic error delays a system shutdown of the computing device; and
firmware executed by the processor to, responsive to the error signal intercept, copy contents of the volatile memory to a non-volatile memory,
wherein the integrated circuit delays the system shutdown of the computing device by a pulse where the error is recoverable or a hold where the error is non-recoverable.

16. The memory module of claim 15 , further comprising the non-volatile memory.

17. The memory module of claim 15 , further comprising a media controller to facilitate the copy of the contents of the volatile memory to the non-volatile memory.

18. The memory module of claim 15 , further comprising an uninterruptible power supply (UPS) to provide power for the copy of the contents of the volatile memory to the non-volatile memory.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Fevrier Thierry
• Heinrich David F
• Hallowell William C
• Fletcher Mark S
• Park Justin Haanbyull
• Engler David W

Classifications

• G06F1/30 Primary

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• G06F2212/311

  In host system · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F1/32

  Means for saving power · CPC title