Increasing the Dynamic Range of an Integrator Based Mutual-Capacitance Measurement Circuit
US-2017336893-A1 · Nov 23, 2017 · US
US10845926B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10845926-B2 |
| Application number | US-201916419074-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 22, 2019 |
| Priority date | Jan 24, 2018 |
| Publication date | Nov 24, 2020 |
| Grant date | Nov 24, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
The present application discloses a capacitance detecting circuit, a touch device and terminal device, which are beneficial for reducing an area of the capacitance detecting circuit, thereby reducing costs of a chip. The capacitance detecting circuit is connected to a measurement capacitor and where it includes a calibration capacitor; a charging and discharging module including a first current source configured to perform charging or discharging on the measurement capacitor, and a second current source configured to perform charging or discharging on the calibration capacitor; an integrator, configured to convert a capacitance signal of the measurement capacitor into a voltage signal; and a control module, configured to control working states of the charging and discharging module and the integrator.
Opening claim text (preview).
What is claimed is: 1. A capacitance detecting circuit, connected to a measurement capacitor, comprising: a calibration capacitor; a charging and discharging module comprising a first current source configured to perform charging on the measurement capacitor, and a second current source configured to perform charging on the calibration capacitor, or the first current source configured to perform discharging on the measurement capacitor, and the second current source configured to perform discharging on the calibration capacitor; an integrator, configured to convert a capacitance signal of the measurement capacitor into a voltage signal; and a control module, configured to control working states of the charging and discharging module and the integrator; wherein the capacitance detecting circuit further comprises a set of charging and discharging switches, a set of clearing switches and a set of integrating switches, and the integrator comprises an integrating capacitor and an amplifier; the control module is configured to: in a charge clearing phase, clear charges stored on the integrating capacitor through the set of clearing switches; in a charging and discharging phase, control the first current source to perform charging or discharging on the measurement capacitor through the set of charging and discharging switches and control the second current source to perform charging or discharging on the calibration capacitor through the set of charging and discharging switches, wherein in the charging and discharging phase, the measurement capacitor is charged or discharged until a voltage is equal to a reference voltage, a charging duration of the calibration capacitor is equal to a charging duration of the measurement capacitor, or a discharging duration of the calibration capacitor is equal to a discharging duration of the measurement capacitor; and in a charge transferring phase, control a part of charges stored on the calibration capacitor to be transferred to the integrating capacitor through the set of integrating switches; wherein the set of charging and discharging switches comprises a first switch, a second switch, a third switch and a fourth switch, the set of integrating switches comprises a fifth switch, and the set of clearing switches comprises a sixth switch; one end of the first switch is connected to one end of the first current source, the other end of the first current source is connected to a power supply voltage, the other end of the first switch is connected to one end of the measurement capacitor and one end of the third switch, and the other end of the measurement capacitor and the other end of the third switch are grounded; one end of the second switch is connected to one end of the second current source, the other end of the second current source is connected to a power supply voltage, the other end of the second switch is connected to one end of the calibration capacitor and one end of the fourth switch, and the other end of the calibration capacitor and the other end of the fourth switch are grounded; one end of the fifth switch is connected to one end of the calibration capacitor, the other end of the fifth switch is connected to a first input end of the amplifier, and a second input end of the amplifier is configured to input the reference voltage; and the sixth switch is connected in parallel with the integrating capacitor, and the integrating capacitor is connected in parallel with the amplifier; and in the charge clearing phase, the sixth switch is turned on, the first switch, the second switch, the third switch, the fourth switch, and the fifth switch are all turned off, and charges stored on the integrating capacitor are cleared; and the charging and discharging phase comprises a discharging phase and a charging phase, and the discharging phase is prior to the charging phase, wherein in the discharging phase, the third switch and the fourth switch are turned on, the first switch, the second switch, the fifth switch and the sixth switch are all turned off, charges stored on the measurement capacitor and the calibration capacitor are cleared; in the charging phase, the first switch and the second switch are turned on, the third switch, the fourth switch, the fifth switch and the sixth switch are all turned off, the measurement capacitor is charged until the voltage is equal to the reference voltage, and after the measurement capacitor is charged until the voltage is equal to the reference voltage, the first switch and the second switch are turned off; and in the charge transferring phase, the first switch, the second switch, the third switch, the fourth switch and the sixth switch are all turned off, the fifth switch is turned on, and a part of charges on the calibration capacitor are transferred to the integrating capacitor. 2. The capacitance detecting circuit according to claim 1 , wherein a first buffering phase is comprised between the charging and discharging phase and the charge transferring phase, and a second buffering phase is comprised after the charge transferring phase, wherein the first buffering phase and the second buffering phase are used to maintain charges on the measurement capacitor, the calibration capacitor and the integrating capacitor unchanged; wherein in the first buffering phase and the second buffering phase, the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are all turned off. 3. The capacitance detecting circuit according to claim 2 , wherein the control module is further configured to: control the set of charging and discharging switches, the set of integrating switches, and the set of clearing switches to repeatedly execute operations from the charging and discharging phase to the second buffering phase for multiple times. 4. The capacitance detecting circuit according to claim 3 , wherein an output voltage V out of the integrator is: V out = V R - Δ C x I 2 / I 1 C S V R N wherein the V R is the reference voltage, the ΔC x is a variation of a capacitance value of the measurement capacitor with respect to a reference capacitance value, the C S is a capacitance value of the integrating capacitor, the I 1 is a current value of the first current source, the I 2 is a current value of the second current source, and the N is the number of execution times from the charging and discharging phase to the second buffering phase. 5. The capacitance detecting circuit according to claim 1 , wherein the capacitance detecting circuit further comprises a comparator, a first input end of
Measuring capacitance (capacitive sensors G01D5/24) · CPC title
Capacitive touch switches · CPC title
Control or interface arrangements specially adapted for digitisers · CPC title
Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references (G01R33/0035, G01R35/002 take precedence) · CPC title
by capacitive means · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.