Voltage-to-current converter

Patent metadata

Field	Value
Publication number	US-10845832-B2
Application number	US-201916562141-A
Country	US
Kind code	B2
Filing date	Sep 5, 2019
Priority date	Sep 10, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A voltage-to-current converter can be configured to generate a current based on an input voltage and for part of the time use the generated current as the output current of the voltage-to-current converter, and for part of the time use the generated current as a current source for the operation of the voltage-to-current converter. This arrangement can reduce the need for high performance current mirror circuits within the voltage-to-current converter, thereby reducing the cost and complexity of the voltage-to-current converter and improving precision and accuracy.

First claim

The claimed invention is:

1. A V-to-I converter system configured to use a received clock signal having a clock cycle to convert an input voltage to an output current, the V-to-I converter system comprising:
a V-to-I conversion unit configured to receive the clock signal and convert the input to a first current;
wherein for a first portion of the clock cycle, the output current comprises the first current and for at least part of the remainder of the clock cycle, the first current is used as a current source to charge the V-to-I conversion unit.

2. The V-to-I converter system of claim 1 , wherein the V-to-I conversion unit is further configured to receive the clock signal and convert the input voltage to a second current, and
wherein for a second portion of the clock cycle, the output current comprises the second current and for at least part of the remainder of the clock cycle, the second current is used as a current source to charge the V-to-I conversion unit.

3. The V-to-I converter system of claim 1 , wherein the first portion of the clock cycle is approximately 50% of the clock cycle.

4. The V-to-I converter system of claim 2 , wherein the V-to-I conversion unit is further configured to receive the clock signal and convert the input voltage to a third current, and
wherein for a third portion of the clock cycle, the output current comprises the third current and for at least part of the remainder of the clock cycle, the third current is used as a current source to charge the V-to-I conversion unit.

5. The V-to-I converter system of claim 4 , wherein the first portion of the clock cycle is approximately 33% of the clock cycle, the second portion of the clock cycle is approximately 33% of the clock cycle and the third portion of the clock cycle is approximately the remaining 33% of the clock cycle.

6. The V-to-I converter system of claim 1 , further comprising a current steering stage configured to:
steer the first current to the output of the V-to-I converter system during the first portion of the clock cycle and steer the first current to act as the current source for the V-to-I conversion unit for at least part of the remainder of the clock cycle.

7. The V-to-I converter system of claim 1 , wherein the V-to-I conversion unit further comprises a first capacitor, and wherein the V-to-I conversion system is configured such that when the first current is used as the current source for the V-to-I conversion unit, the first capacitor is charged by the first current.

8. The V-to-I converter system of claim 1 , wherein the V-to-I conversion unit further comprises a first capacitor, and wherein the V-to-I conversion unit further comprises at least one an integrator circuit configured to generate a control voltage based at least in part on the input voltage and a voltage across the first capacitor.

9. The V-to-I converter system of claim 8 , wherein the at least one integrator circuit is configured to configured to integrate a difference between the input voltage and the voltage across the first capacitor.

10. The V-to-I converter system of claim 8 , wherein the V-to-I conversion unit further comprises a transconductance stage configured to generate the first current based on the control voltage.

11. The V-to-I converter system of claim 10 , wherein the transconductance stage is configured to generate the first current based further on a quiescent current.

12. A method of using a V-to-I converter system configured to use a received clock signal having a clock cycle to convert an input voltage to an output current at an output terminal of the V-to-I converter system, the method comprising:
converting, using a V-to-I conversion unit of the V-to-I converter system, the input voltage to a first current, wherein the V-to-I conversion unit is configured to receive the clock signal; and
during a first portion of a clock cycle, steering the first current to the output terminal of the V-to-I converter system and during at least part of the remainder of the clock cycle, steering the first current so as to be used as a current source to charge the V-to-I conversion unit.

13. The method of claim 12 , further comprising:
converting, using the V-to-I conversion unit of the V-to-I converter system, the input voltage to a second current, wherein the V-to-I conversion unit is configured to receive the clock signal; and
during a second portion of the clock cycle, steering the second current to the output terminal of the V-to-I converter system and during at least part of the remainder of the clock cycle, steering the second current so as to be used as a current source to charge the V-to-I conversion unit.

14. The method of claim 13 , further comprising:
converting, using a V-to-I conversion unit of the V-to-I converter system, the input voltage to a third current, wherein the V-to-I conversion unit is configured to receive the clock signal; and
during a third portion of the clock cycle, steering the third current to the output terminal of the V-to-I converter system and during at least part of the remainder of the clock cycle, steering the third current so as to be used as a current source to charge the V-to-I conversion unit.

15. The method of claim 12 , wherein the first portion of the clock cycle is approximately 50% of the clock cycle.

16. The method of claim 12 , wherein the first portion of the clock cycle is approximately 33% of the clock cycle.

17. A V-to-I converter system configured to use a received clock signal having a clock cycle to convert an input voltage to an output current, the converter system comprising:
a V-to-I conversion unit comprising:
a first capacitor; and
a second capacitor,
wherein the V-to-I conversion unit is configured to generate a first current and a second current based on the input voltage and charges accumulated in the first capacitor and second capacitor; and
a switch stage configured to:
receive the first current and the second current;
steer the first current to the first input of the V-to-I conversion unit during a first portion of the clock cycle in order to charge the first capacitor during the first portion of the clock cycle and steer the first current to an output terminal of the V-to-I converter system during at least part of the remaining portion of the clock cycle; and
steer the second current to the second input of the V-to-I conversion unit during a second portion of the clock cycle in order to charge the second capacitor during the second portion of the clock cycle and steer the second current to the output terminal of the V-to-I converter system during at least part of the remaining portion of the clock cycle;

wherein the output current is the current output from the output terminal of the converter system.

18. The system of claim 17 , wherein the V-to-I conversion unit further comprises an integrator circuit configured to generate a control voltage by:
integrating a difference between the input voltage and a voltage across the first capacitor during at least part of the first portion of the clock cycle; and
integrating a difference between the input voltage and a voltage across the second capacitor during at least part of the second portion of the clock cycle.

19. The system of claim 18 , further comprising a transconductance stage configured to generate the first current and the second current based at least in part on the control voltage.

20. The system of claim 17 , wherein the first portion of the clock cycle approximately 50% of the clock cycle and the se

Assignees

• Analog Devices International Unlimited Co

Inventors

• Hurwitz Jonathan Ephraim David

Classifications

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title

• G05F3/30

  Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) · CPC title

• G05F1/468

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• G01R22/068

  Arrangements for indicating or signaling faults · CPC title