Display device

Patent metadata

Field	Value
Publication number	US-10845639-B2
Application number	US-201816235047-A
Country	US
Kind code	B2
Filing date	Dec 28, 2018
Priority date	Dec 29, 2017
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

Disclosed herein is a display device for increasing the transmittance of R, G, and B sub-pixels and reducing a transmittance of W sub-pixel through a pixel asymmetric design. To this end, the display device has a pixel asymmetric structure in which W sub-pixel has a different area from R, G and B sub-pixels. As a result, as the display device has an asymmetric structure in which the areas of W, R, G, and B sub-pixels are different from one another, particularly, an asymmetric structure in which the area of W sub-pixel is reduced and the area of R sub-pixel is increased. Such design has a structural advantage that the transmittance of R, G, and B sub-pixels can be increased and the transmittance of W sub-pixel can be lowered so that it is possible to correspond the product specifications in various ways.

First claim

What is claimed is:

1. A display device, comprising:
a thin film transistor substrate including a plurality of white (W), red (R), green (G), and blue (B) sub-pixels arranged in respective regions formed adjacent to overlapping locations of a plurality of gate lines and a plurality of data lines; and
a color filter substrate which faces the thin film transistor substrate and includes a plurality of W, R, G, and B sub-color filters arranged corresponding to the plurality of W, R, G, and B sub-pixels, respectively,
wherein two gate lines arranged in a respective one of the W sub-pixels have a symmetric structure protruding inward with respect to the W sub-pixel, and
wherein two gate lines arranged in any one of R, G, and B sub-pixels have a symmetric structure protruding outward with respect to the any one of R, G, and B sub-pixels.

2. The display device of claim 1 ,
wherein the respective areas of the R, G, and B sub-pixels are larger than the area of each of the W sub-pixels.

3. The display device of claim 1 ,
wherein each of the W sub-pixels has a first area,
wherein one of the R, G, and B sub-pixels has a second area that is larger than the first area, and
wherein a remaining two of the R, G, and B sub-pixels have a third area that is larger than the first area and smaller than the second area.

4. The display device of claim 3 , wherein the second area is within a range of 10% to 15% larger than the third area.

5. The display device of claim 1 , wherein two sub-pixels of the plurality of W, R, G, and B sub-pixels form one unit pixel.

6. The display device of claim 5 , wherein a W sub-pixel and an adjacent R sub-pixel in a first row form a first unit pixel, and a G sub-pixel and an adjacent B sub-pixel in the first row form a second unit pixel.

7. The display device of claim 6 , wherein a G sub-pixel and an adjacent B sub-pixel in a second row form a third unit pixel, and a W sub-pixel and an adjacent R sub-pixel in the second row form a fourth unit pixel.

8. The display device of claim 7 , wherein the first and third unit pixels are adjacent to one another along a direction transverse to a row direction, and the second and fourth unit pixels are adjacent to one another along the direction transverse to the row direction.

9. The display device of claim 5 , wherein the plurality of W, R, G, and B sub-pixels includes a first row parallel to the plurality of gate lines in which the sub-pixels are arranged in a repeating order of W, R, G, and B sub-pixels, and a second row parallel to the first row in which the sub-pixels are arranged in a repeating order of G, B, W, and R sub-pixels, the G sub-pixels of the second row being adjacent to the W sub-pixels of the first row along a direction transverse to the plurality of gate lines.

10. The display device of claim 1 ,
wherein the thin film transistor substrate comprises:
the plurality of gate lines arranged along a first direction on a first substrate;
the plurality of data lines arranged along a second direction overlapping the first direction;
a plurality of thin film transistors arranged adjacent to overlapping locations between the plurality of gate lines and the plurality of data lines, respectively;
a plurality of pixel electrodes respectively connected to the plurality of thin film transistors, and arranged in the plurality of W, R, G, and B sub-pixels, respectively; and
a common electrode arranged between the plurality of thin film transistors and the plurality of pixel electrodes, the common electrode at least partially overlapped with the plurality of pixel electrodes.

11. The display device of claim 10 ,
wherein each of the plurality of thin film transistors comprises:
a gate electrode that is a part of one of the gate lines;
a source electrode that is a part of one of the data lines;
a drain electrode spaced apart from the source electrode; and
a semiconductor layer having a first end connected to the source electrode and a second end connected to the drain electrode, a part of the semiconductor layer overlapping with the gate electrode.

12. The display device of claim 10 , wherein the thin film transistor substrate further comprises a touch signal line overlapped with the data line and electrically connected to the common electrode.

13. The display device of claim 1 ,
wherein the color filter substrate comprises:
the plurality of W, R, G, and B sub-color filters arranged at positions corresponding to the plurality of W, R, G, and B sub-pixels, respectively;
a black matrix arranged at a boundary area of the plurality of W, R, G, and B sub-color filters;
an overcoat layer covering the plurality of W, R, G, and B sub-color filters and the black matrix; and
a column spacer arranged at a position corresponding to the black matrix on the overcoat layer and corresponding to an overlapping portion between the plurality of gate lines and the plurality of data lines.

14. The display device of claim 1 ,
wherein the W sub-pixels have a different area than the R, G, and B sub-pixels.

15. The display device of claim 1 ,
wherein the plurality of W, R, G, and B sub-pixels includes a first row parallel to the plurality of gate lines in which the sub-pixels are arranged in a repeating order of W, G, B and R sub-pixel, and a second row parallel to the first row in which the sub-pixels are arranged in a repeating order of B, R, W, and G sub-pixels, the B sub-pixels of the second row being adjacent to the W sub-pixels of the first row along a direction transverse to the plurality of gate lines.

Assignees

• Lg Display Co Ltd

Inventors

• Lee Taekeun
• Kim Sunggyu

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F2201/52

  RGB geometrical arrangements · CPC title

• G02F1/1335 Primary

  Structural association of cells with optical devices, e.g. polarisers or reflectors · CPC title

• G02F1/134345

  Subdivided pixels, e.g. for grey scale or redundancy · CPC title