Compact Fluid Analysis Device and Method to Fabricate
US-2015093816-A1 · Apr 2, 2015 · US
US10843922B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10843922-B2 |
| Application number | US-201514824695-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 12, 2015 |
| Priority date | May 22, 2013 |
| Publication date | Nov 24, 2020 |
| Grant date | Nov 24, 2020 |
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The present disclosure relates to a device for analyzing a fluid sample. In one aspect, the device includes a fluidic substrate that comprises a micro-fluidic component embedded in the fluidic substrate configured to propagate a fluid sample via capillary force through the device and a means for providing a fluid sample connected to the micro-fluidic component. The device also includes a lid attached to the fluidic substrate at least partly covering the fluidic substrate and at least partly closing the micro-fluidic component. The fluidic substrate may be a silicon fluidic substrate and the lid may be a CMOS chip. In another aspect, embodiments of the present disclosure relate to a method for fabricating such a device, and the method may include providing a fluidic substrate, providing a lid, and attaching, through a CMOS compatible bonding process, the fluidic substrate to the lid to close the fluidic substrate at least partly.
Opening claim text (preview).
The invention claimed is: 1. A method for fabricating a device for analyzing a fluid sample, comprising: providing a fluidic substrate including fine structures comprising micro-pillars, wherein the fine structures are configured to create a capillary action that propagates the fluid sample through at least a portion of the device and wherein the micro-pillars have a lateral dimension ranging from 1 μm to 20 μm and an aspect ratio ranging from 20 to 50; and coarse structures configured to store larger volumes of fluid than the fine structures; providing a Complimentary Metal-Oxide Semiconductor (CMOS) chip; and attaching the fluidic substrate to the CMOS chip using a CMOS compatible bonding process so that the CMOS chip partly covers the fluidic substrate, wherein a portion of the CMOS chip forms an overhang, wherein the portion of the CMOS chip comprises an I/O pad, wherein a portion of the fluidic substrate including the micro-fluidic component is not covered, and wherein the uncovered portion of the micro-fluidic component comprises at least one reagent application zone. 2. The method according to claim 1 , wherein providing the fluidic substrate comprises: providing a silicon substrate; providing an oxide mask; patterning the oxide mask to create the fine structures in the oxide mask; providing a protection layer to protect the patterned oxide mask; patterning the coarse structures; etching the coarse structures; growing oxide for protecting the coarse structures; removing the protection layer; etching the fine structures; and removing the oxide. 3. The method according to claim 1 , wherein providing the fluidic substrate further comprises: providing a silicon substrate; providing a plurality of masks over the silicon substrate; and using the plurality of masks to create microfluidic structures of different depths. 4. The method according to claim 3 , wherein providing the fluidic substrate further comprises: providing a first oxide mask over the silicon substrate; patterning first microfluidic structures in the first oxide mask; etching the first microfluidic structures in the silicon substrate to a first depth; providing a second oxide mask over the silicon substrate; patterning second microfluidic structures in the second oxide mask; and etching the second microfluidic structures in the silicon substrate to a second depth, wherein the first depth is different than the second depth. 5. The method according to claim 1 , further comprising coating, at least partially, one or more surfaces of the fluidic substrate or the CMOS chip to modify surface interactions with the fluid sample. 6. The method according to claim 1 , wherein the portion of the CMOS chip does not cover the fluidic substrate. 7. The method according to claim 1 , wherein the CMOS compatible bonding process includes bonding the fluidic substrate to the CMOS chip using a lithographically patterned polymer. 8. The method of claim 1 , wherein providing the CMOS chip further comprises: providing a silicon substrate; fabricating a transistor layer over the silicon substrate; and providing an interconnection layer over the transistor layer, wherein the interconnection layer includes at least one metal layer. 9. The method of claim 8 , wherein providing the CMOS chip further comprises coupling one or more components to the interconnection layer, wherein the one or more components include one or more of a biocompatible electrode, an electrode configured to manipulate a fluid, circuitry configured for data communication, a temperature sensor, a heater electrode, a fluid sensor, an electrode for fluid viscosity control, a bonding layer, or an I/O pad. 10. The method of claim 1 , wherein at least one of providing the fluidic substrate or providing the CMOS chip includes etching one or more through-holes in the fluidic substrate or the CMOS chip. 11. The method of claim 1 , wherein the CMOS compatible bonding process includes one or more of a die to wafer bonding process or a wafer to wafer bonding process. 12. The method of claim 1 , wherein the fluidic substrate is attached directly to the CMOS chip, and wherein the CMOS chip is in direct contact with the fluid sample when the fluid sample is present in the device. 13. The method of claim 1 , wherein the fluidic substrate comprises at least one optical waveguide. 14. The method of claim 13 , wherein the at least one waveguide is configured to allow optical excitation and sensing of the fluid sample.
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