Method and system for carrying out timing related tasks

Patent metadata

Field	Value
Publication number	US-10841885-B2
Application number	US-201716464264-A
Country	US
Kind code	B2
Filing date	Nov 24, 2017
Priority date	Nov 25, 2016
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

Embodiments of the present invention provide a method and system for timing related tasks in IoT systems, for example, in relation to synchronisation of clocks and timestamping. It is desirable that the method and system is able to withstand external tampering in a manner which does not jeopardise the accuracy and integrity of time related tasks in the IoT systems.

First claim

The invention claimed is:

1. A system for determining a timestamp using powerline voltage fluctuations, the system including one or more electronic devices configured to:
determine, at a first node, a first voltage fluctuation sequence;
determine, at a second node, the second node being on a power grid of the first node, a second voltage fluctuation sequence; and
compare, data of the first and second voltage fluctuation sequences, to determine a clock offset between the first and second nodes,
wherein each fluctuation sequence is a timestamp.

2. The system of claim 1 , wherein each node includes a sensor to determine voltage fluctuations from either the node or a source in close proximity to the node.

3. The system of claim 1 , wherein the second node includes a timing apparatus for timestamping the clock offset, the timing apparatus being either a global navigation satellite system (GNSS) receiver or an atomic clock.

4. The system of claim 1 , wherein the clock offset is determined using the formula:
i *=argmin iϵ[1,m−n+1] dissimilarity( f,g [ i:i+n− 1])

5. The system of claim 1 , wherein the second node further includes a voltage sensor for determining voltage fluctuations at a power outlet of the second node.

6. The system of claim 1 , wherein data of the first and second voltage fluctuation sequences are processed to remove DC bias and high frequency spikes.

7. The system of claim 1 , wherein the voltage fluctuations result from either ENF or EMR fluctuations.

8. A data processor implemented method for determining a timestamp using powerline voltage fluctuations, the method including:
determining, at a first node, a first voltage fluctuation sequence;
determining, at a second node, the second node being on a power grid of the first node, a second voltage fluctuation sequence; and
comparing, data of the first and second voltage fluctuation sequences, to determine a clock offset between the first and second nodes,
wherein each fluctuation sequence is a timestamp.

9. The method of claim 8 , wherein each node includes a sensor to determine voltage fluctuations.

10. The method of claim 8 , wherein the second node includes a timing apparatus for timestamping the clock offset, the timing apparatus being either a global navigation satellite system (GNSS) receiver or an atomic clock.

11. The method of claim 8 , wherein the clock offset is determined using the formula:
i *=argmin iϵ[1,m−n+1] dissimilarity( f,g [ i:i+n− 1])

12. The method of claim 8 , wherein the second node further includes a voltage sensor for determining voltage fluctuations at a power outlet of the second node.

13. The method of claim 8 , wherein the data of the first and second voltage fluctuation sequences is processed to remove DC bias and high frequency spikes.

14. The method of claim 8 , wherein the voltage fluctuations result from either ENF or EMR fluctuations.

15. A non-transitory computer readable storage medium embodying thereon a program of computer readable instructions which, when executed by one or more processors of a first node in communication with at least one other processor of a second node, cause the first node to carry out a method for determining a timestamp using powerline voltage fluctuations, the method embodying the steps of:
receiving, at a first node, first data of a first voltage fluctuation sequence at a second node, the second node being on a power grid of the first node;
determining, at the first node, second data of a second voltage fluctuation sequence; and
comparing, the first and second data, to determine a clock offset between the first and second nodes,
wherein each fluctuation sequence is a timestamp.

16. A system for synchronising clocks, the system including one or more electronic devices that:
determine, at a first node, a first node marker and a first node clock value;
transmit, from the first node, a first data packet including the first node clock value and the first node marker;
determine, at a second node, a second node marker and a second node clock value;
receive, at the second node, the first data packet;
synchronise, at the second node, both the first node clock value and the second node clock value, and
determine, at the second node, an offset between the first node clock value and the second node clock value,
wherein the respective node markers are determined from minute fluctuations of a cycle length of an electric voltage signal at each respective node.

17. The system of claim 16 , the system including one or more electronic devices that further transmit, from the second node, a second data packet including the offset.

18. The system of claim 16 , wherein each respective marker is a vector of successive AC cycle lengths of the electric voltage signal at each respective node.

19. The system of claim 16 , the system including one or more electronic devices that further determine, at the second node, of a power grid phase of the first node, wherein determination of the power grid phase includes use of a decoding algorithm.

Assignees

• Univ Singapore Technology & Design
• Illinois At Singapore Pte Ltd

Inventors

• Yau David K Y
• Li Yang
• Tan Rui
• Viswanathan Sreejaya

Classifications

• G06F2218/16

  by matching signal segments · CPC title

• H04L7/0012

  by comparing receiver clock with transmitter clock · CPC title

• H04W56/00 Primary

  Synchronisation arrangements · CPC title

• H04W56/001 Primary

  Synchronization between nodes · CPC title

• G01R29/18

  Indicating phase sequence; Indicating synchronism · CPC title