High-speed receiver architecture

Patent metadata

Field	Value
Publication number	US-10841013-B2
Application number	US-201916674957-A
Country	US
Kind code	B2
Filing date	Nov 5, 2019
Priority date	Oct 3, 2005
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

First claim

What is claimed is:

1. A receiver device, the device comprising:
an interleaved analog-to-digital converter (ADC) configured to generate signal samples from an input signal, the interleaved ADC including
an analog demultiplexer configured to receive the input signal;
a plurality of ADC channels electrically coupled to the analog demultiplexer, each of the plurality of ADC channels having an input track-and-hold stage coupled to the analog demultiplexer and an ADC stage electrically coupled to the input track-and-hold stage; and
a digital retimer electrically coupled to the ADC stage of each of the plurality of ADC channels;
wherein the interleaved ADC is configured in a sub-radix architecture wherein the ADC stage is configured to produce one or more redundant bits for error correction.

2. The device of claim 1 wherein the analog demultiplexer is configured to demultiplex and time interleave the input signal to the plurality of ADC channels; and
wherein the digital retimer is configured to retime and multiplex signals from the plurality of ADC channels into one or more higher data rate signals.

3. The device of claim 1 wherein each of the ADC stages of the plurality of ADC channels includes a plurality of low resolution ADC stages.

4. The device of claim 3 wherein each low resolution ADC stage includes
a 1-bit ADC electrically coupled to an input of the ADC stage;
a 1-bit digital-to-analog converter (DAC) electrically coupled to the 1-bit ADC;
an analog subtractor electrically coupled to the 1-bit DAC and the input of the ADC stage;
a residue amplifier electrically coupled to the analog subtractor; and
a track-and-hold circuit electrically coupled to the residue amplifier.

5. The device of claim 4 wherein each residue amplifier of the low resolution ADC stages includes an open-loop amplifier configured to be calibrated based on a look-up table (LUT).

6. The device of claim 3 wherein the plurality of low resolution ADC stages has more stages than there are bits in the input signal.

7. A method for operating a receiver device, the method comprising:
demultiplexing, by an analog demultiplexer of an interleaved analog-to-digital converter (ADC), an input signal to a plurality of ADC channels of the interleaved ADC;
holding, by an input track-and-hold stage of each of the plurality of ADC channels coupled to the analog demultiplexer, the input signal;
converting, by an ADC stage of each of the plurality of ADC channels coupled to the input track-and-hold stage, the input signal; and
retiming, by a digital retimer of the interleaved ADC coupled to the plurality of ADC channels, the input signal;
wherein converting the input signal includes producing, by the ADC stage configured in a sub-radix architecture, one or more redundant bits for error correction.

8. The method of claim 7 wherein demultiplexing the input signal includes time interleaving the input signal to the plurality of ADC channels; and
wherein retiming the input signal includes multiplexing the plurality of ADC channels into one or more higher data rate signals.

9. The method of claim 7 wherein each of the ADC stages of the plurality of ADC channels comprises a plurality of low resolution ADC stages.

10. The method of claim 9 wherein converting the input signal by the plurality of low resolution ADC stages includes
for a respective stage of the plurality of low resolution ADC stages:
determining, by a 1-bit ADC coupled to an input of the respective low resolution ADC stage, a 1-bit decision on the input signal;
determining, by a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit ADC, a contribution voltage from the input signal;
subtracting, by an analog subtractor coupled to the 1-bit DAC and the input of the respective low resolution ADC stage, the contribution voltage from the input signal to determine a residue;
multiplying, by a residue amplifier coupled to the analog subtractor, the residue by a gain value; and
holding, by a track-and-hold circuit coupled to the residue amplifier, the residue.

11. The method of claim 1 wherein the residue amplifier comprises an open loop amplifier calibrated based on a look-up table (LUT).

12. A transceiver device, the device comprising:
a transmitter device;
a channel having a first end and a second end, the first end being coupled to the transmitter device; and
a receiver device coupled the second end of the channel, the receiver device including an interleaved analog-to-digital converter (ADC) configured to generate signal samples from an input signal received from the transmitter over the channel;
wherein the interleaved ADC includes
an analog demultiplexer configured to receive the input signal;
a plurality of ADC channels electrically coupled to the analog demultiplexer, each of the plurality of ADC channels having an input track-and-hold stage coupled to the analog demultiplexer and an ADC stage electrically coupled to the input track-and-hold stage; and
a digital retimer electrically coupled to the ADC stage of each of the plurality of ADC channels;
wherein the interleaved ADC is configured in a sub-radix architecture wherein the ADC stage is configured to produce one or more redundant bits for error correction.

13. The device of claim 12 wherein each of the ADC stages of the plurality of ADC channels includes a plurality of low resolution ADC stages.

14. The device of claim 13 wherein each low resolution ADC stage includes
a 1-bit ADC electrically coupled to an input of the ADC stage;
a 1-bit digital-to-analog converter (DAC) electrically coupled to the 1-bit ADC;
an analog subtractor electrically coupled to the 1-bit DAC and the input of the ADC stage;
a residue amplifier electrically coupled to the analog subtractor; and
a track-and-hold circuit electrically coupled to the residue amplifier.

15. The device of claim 14 wherein each residue amplifier of the low resolution ADC stages includes an open-loop amplifier configured to be calibrated based on a look-up table (LUT).

16. The device of claim 13 wherein the plurality of low resolution ADC stages has more stages than there are bits in the input signal.

17. A receiver device, the device comprising:
an interleaved analog-to-digital converter (ADC) configured to generate signal samples from an input signal, the interleaved ADC including
an analog demultiplexer configured to receive the input signal;
a plurality of ADC channels electrically coupled to the analog demultiplexer, each of the plurality of ADC channels having an input track-and-hold stage coupled to the analog demultiplexer and an ADC stage electrically coupled to the input track-and-hold stage; and
a digital retimer electrically coupled to the ADC stage of each of the plurality of ADC channels;
wherein each of the ADC stages of the plurality of ADC channels includes a plurality of low resolution ADC stages; and
wherein each low resolution ADC stage includes
a 1-bit ADC electrically coupled to an input of the ADC stage;
a 1-bit digital-to-analog converter (DAC) electrically coupled to the 1-bit ADC;
an analog subtractor electrically coupled to the 1-bit DAC and the input of the ADC stage;
a residue amplifier electrically coupled to the analog subtractor; and
a track-and-hold circuit electrically coupled to the residue amplifier.

18. The device of claim 17 wherein the analog demultiplexer is configured to demultiplex and time interleave the input signal to the plurality of ADC channels; and
wherein the digital retimer is configured to retime and

Assignees

• Inphi Corp

Inventors

• Agazzi Oscar Ernesto
• Crivelli Diego Ernesto
• Carrer Hugo Santiago
• Hueda Mario Rafael
• Luna German Cesar Augusto
• Grace Carl

Classifications

• H04B10/6971 Primary

  using equalisation · CPC title

• H04L2025/03477

  not time-recursive · CPC title

• H04L25/025

  using least-mean-square [LMS] method · CPC title

• H04L25/0202

  Channel estimation · CPC title

• H04B10/5059 Primary

  using a feed-forward signal generated by analysing the optical or electrical input · CPC title