Suppression of noise of delta-sigma modulators

Patent metadata

Field	Value
Publication number	US-10840940-B2
Application number	US-201916706035-A
Country	US
Kind code	B2
Filing date	Dec 6, 2019
Priority date	Dec 20, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a near-zero asymmetric quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter such that the quantized output signal has a plurality of quantization levels, wherein the plurality of quantization levels are asymmetric to zero.

First claim

What is claimed is:

1. A delta-sigma modulator comprising:
a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal; and
a near-zero asymmetric quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter such that the quantized output signal has a plurality of quantization levels, wherein the plurality of quantization levels are asymmetric to zero.

2. The delta-sigma modulator of claim 1 , wherein the plurality of levels comprises a first level and a second level which are the nearest levels to zero and a value of the first level plus a value of the second level is not equal to zero.

3. The delta-sigma modulator of claim 1 , wherein:
the plurality of levels comprise a first level, a second level, and a third level which are the nearest levels to zero;
the first level is lesser than the second level which is in turn lesser than the third level;
a value of the first level plus a value of the second level is not equal to zero;
the value of the second level plus a value of the third level is not equal to zero; and
the value of the first level plus the value of the third level is not equal to two times the value of the second level.

4. A delta-sigma modulator comprising:
a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal, wherein the loop filter comprises one or more integrator stages comprising a first integrator stage;
a quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter such that the quantized output signal has a plurality of quantization levels; and
a biasing block configured to:
calculate a fractional part of a state variable associated with the first integrator stage;
determine if the fractional part has a desired value; and
responsive to the fractional part being outside of the desired value, actively bias the state variable to cause the fractional part to have the desired value in order to cause the delta-sigma modulator to have a desired noise profile.

5. The delta-sigma modulator of claim 4 , wherein the biasing block is configured to calculate the fractional part as a remainder of an integrated value of the first integrator stage divided by a smallest positive quantization level of the quantizer.

6. The delta-sigma modulator of claim 4 , wherein the biasing block is configured to actively bias the state variable by adding a predefined amount to the state variable to cause the state variable to have a fractional part closer to or within the desired value.

7. The delta-sigma modulator of claim 4 , wherein the desired noise profile comprises at least one of:
a lowest noise in a band of interest;
a flattest low-frequency component; and
a lack of significant fluctuation under 20 hertz.

8. The delta-sigma modulator of claim 4 , wherein the quantizer comprises a near-zero asymmetric quantizer wherein the quantized output signal has a plurality of quantization levels, and wherein the plurality of quantization levels are asymmetric to zero.

9. The delta-sigma modulator of claim 8 , wherein the plurality of levels comprises a first level and a second level which are the nearest levels to zero and a value of the first level plus a value of the second level is not equal to zero.

10. The delta-sigma modulator of claim 8 , wherein:
the plurality of levels comprises a first level, a second level, and a third level which are the nearest levels to zero;
the first level is lesser than the second level which is in turn lesser than the third level;
a value of the first level plus a value of the second level is not equal to zero;
the value of the second level plus a value of the third level is not equal to zero; and
the value of the first level plus the value of the third level is not equal to two times the value of the second level.

11. A method comprising:
generating, with a loop filter, an intermediate signal responsive to an input signal to the loop filter; and
quantizing, with a near-zero asymmetric quantizer, the intermediate signal into a quantized output signal which is fed back as an input to the loop filter such that the quantized output signal has a plurality of quantization levels, wherein the plurality of quantization levels are asymmetric to zero.

12. The method of claim 11 , wherein the plurality of levels comprises a first level and a second level which are the nearest levels to zero and a value of the first level plus a value of the second level is not equal to zero.

13. The method of claim 11 , wherein:
the plurality of levels comprises a first level, a second level, and a third level which are the nearest levels to zero;
the first level is lesser than the second level which is in turn lesser than the third level;
a value of the first level plus a value of the second level is not equal to zero;
the value of the second level plus a value of the third level is not equal to zero; and
the value of the first level plus the value of the third level is not equal to two times the value of the second level.

14. A method comprising:
generating, with a loop filter comprising one or more integrator stages comprising a first integrator stage, an intermediate signal responsive to an input signal to the loop filter;
quantizing, with a quantizer, the intermediate signal into a quantized output signal which is fed back as an input to the loop filter such that the quantized output signal has a plurality of quantization levels;
calculating a fractional part of a state variable associated with the first integrator stage;
determining if the fractional part has a desired value; and
responsive to the fractional part being outside of the desired value, actively biasing the state variable to cause the fractional part to have the desired value in order to cause the delta-sigma modulator to have a desired noise profile.

15. The method of claim 14 , further comprising calculating the fractional part as a remainder of an integrated value of the first integrator stage divided by a smallest positive quantization level of the quantizer.

16. The method of claim 14 , further comprising actively biasing the state variable by adding a predefined amount to the state variable to cause the state variable to have a fractional part closer to or within the desired value.

17. The method of claim 14 , wherein the desired noise profile comprises at least one of:
a lowest noise in a band of interest;
a flattest low-frequency component; and
a lack of significant fluctuation under 20 hertz.

18. The method of claim 14 , wherein the quantizer comprises a near-zero asymmetric quantizer wherein the quantized output signal has a plurality of quantization levels, and wherein the plurality of quantization levels are asymmetric to zero.

19. The method of claim 18 , wherein the plurality of levels comprises a first level and a second level which are the nearest levels to zero and a value of the first level plus a value of the second level is not equal to zero.

20. The method of claim 18 , wherein:
the plurality of levels comprises a first level, a second level, and a third level which are the nearest levels to zero;
the first level is lesser than the second level which is in turn lesser than the third level;
a value of the first level plus a value of the second level is not

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Yin Leyi
• Melanson John L
• Shum Wai-Shun
• Fei Xiaofan

Classifications

• H03M3/506

  the final digital/analogue converter being constituted by a pulse width modulator · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H03M1/06

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M3/448 Primary

  by removing part of the zeroes, e.g. using local feedback loops · CPC title

• H03M3/414

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title