A/D conversion circuit with shifted encode values

Patent metadata

Field	Value
Publication number	US-10840938-B2
Application number	US-201916583757-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Dec 21, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

An A/D conversion circuit converts an analog signal into numerical data. The A/D conversion circuit includes: a pulse delay circuit that includes an odd number of delay units connected in series, and inverting and delaying a pulse signal, and that changes the numeral number of the delay units which the pulse signal passes through in accordance with a value of the analog signal; latch circuits that synchronize the pulse signal with sampling clocks, and latch the pulse signal; encoders that set a position of the pulse signal to the numerical data by circulating encode values periodically set in order from an initial value to a final value to synchronously sample the encode values; subtractors that calculate each of differences between a previous value and a current value; and an adder that adds subtraction results. The encode values are set to be shifted between at least two encoders.

First claim

The invention claimed is:

1. An A/D conversion circuit configured to convert an analog signal into numerical data, the A/D conversion circuit comprising:
a pulse delay circuit that
includes a plurality of delay units that
are connected in series, and
are configured to invert and delay a pulse signal, and

is configured to change a numerical number of the delay units which the pulse signal passes through in accordance with a value of the analog signal;

a plurality of latch circuits configured to
synchronize the pulse signal delayed by the pulse delay circuit with a plurality of sampling clocks, and
latch the pulse signal;

a plurality of encoders each of which is configured to set a position of the pulse signal to the numerical data by circulating encode values periodically set in order from an initial value to a final value to synchronously sample the encode values based on the pulse signal latched by the plurality of latch circuits and the plurality of sampling clocks;
a plurality of subtractors configured to calculate each of differences between a previous value corresponding to the numerical data of the encoders and a current value corresponding to the numerical data of the encoders, the numerical data being synchronously sampled by successive sampling clocks; and
an adder configured to add subtraction results of the plurality of subtractors to output digital data, wherein:
the encode values are set to be shifted from each other between at least two encoders of the plurality of encoders; and
a numerical number of the delay units connected in series is odd.

2. The A/D conversion circuit according to claim 1 , wherein:
shift amounts of the encode values are equally set between the plurality of encoders.

3. The A/D conversion circuit according to claim 2 , wherein:
at a same timing, each of the shift amounts of the encode values corresponds to a difference value between one of the encode values in one of the encoders and another one of the encode values in another one of the encoders.

4. The A/D conversion circuit according to claim 2 , wherein:
the shift amounts correspond to a value obtained by dividing the numerical number of the delay units by a numerical number of a clock edge shift of the sampling clock.

5. The A/D conversion circuit according to claim 1 , wherein:
the plurality of encoders include at least two encoders.

6. The A/D conversion circuit according to claim 1 , wherein:
each of the subtraction results corresponds to each of the differences in each of the subtractors.

7. An A/D conversion circuit configured to convert an analog signal into numerical data, the A/D conversion circuit comprising:
a first pulse delay circuit that
includes a plurality of first delay units that
are connected in series, and
are configured to invert and delay a pulse signal, and

is configured to change a numerical number of the first delay units which the pulse signal passes through in accordance with a value of the analog signal;

a plurality of first latch circuits configured to
synchronize the pulse signal delayed by the first pulse delay circuit with a plurality of sampling clocks, and
latch the pulse signal;

a plurality of first encoders each of which configured to set a position of the pulse signal to the numerical data by sampling first encode values periodically set from a first initial value to a first final value based on the pulse signal latched by the plurality of first latch circuits and the plurality of sampling clocks;
a plurality of first subtractors configured to calculate each of differences between a previous value corresponding to numerical data of the first encoders and a current value corresponding to the numerical data of the first encoders, the numerical data being sampled by successive sampling clocks;
a second pulse delay circuit that
includes a plurality of second delay units that
are connected in series, and
are configured to invert and delay the pulse signal, and

is configured to change a numerical number of the second delay units which the pulse signal passes through in accordance with the value of the analog signal;

a plurality of second latch circuits configured to
synchronize the pulse signal delayed by the second pulse delay circuit with the plurality of sampling clocks, and
latch the pulse signal;

a plurality of second encoders each of which is configured to set a position of the pulse signal to the numerical data by sampling second encode values periodically set from a second initial value to a second final value based on the pulse signal latched by the plurality of second latch circuits and the plurality of sampling clocks;
a plurality of second subtractors configured to calculate each of differences between a previous value of numerical data of the second encoders and a current value of the numerical data of the second encoders, the numerical data being sampled by the successive sampling clocks; and
an adder configured to output the numerical data by adding subtraction results of the plurality of first subtractors and adding subtraction results of the plurality of second subtractors, wherein:
the first encode values are set to be shifted from each other between the at least two encoders;
the second encode values are set to be shifted between the at least two second encoders of the plurality of second encoders;
a numerical number of the first delay units connected in series is defined as (2 n −(2x−1));
a numerical number of the second delay units connected in series is defined as (2 n +(2x−1));
n of (2 n −(2x−1)) or (2 n +(2x−1)) is a numeral number equal to or more than 1; and
x of (2 n −(2x−1)) or (2 n +(2x−1)) is a numeral number equal to or more than 1.

8. The A/D conversion circuit according to claim 7 , wherein:
shift amounts of the first encode values are equally set between the plurality of first encoders; and
shift amounts of the second encode values are equally set between the plurality of second encoders.

9. The A/D conversion circuit according to claim 7 , wherein:
the plurality of first encoders include at least two first encoders; and
the plurality of second encoders include at least two second encoders.

Assignees

• Denso Corp

Inventors

• Watanabe Takamoto

Classifications

• H03M1/502 Primary

  using tapped delay lines · CPC title

• H03M1/1255

  Synchronisation of the sampling frequency or phase to the input frequency or phase · CPC title

• H03M1/60 Primary

  with intermediate conversion to frequency of pulses · CPC title

• H03M1/645

  for position encoding, e.g. using resolvers or synchros (H03M1/485 takes precedence) · CPC title

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title