Digital to analog and analog to digital converter

Patent metadata

Field	Value
Publication number	US-10840931-B2
Application number	US-201916673095-A
Country	US
Kind code	B2
Filing date	Nov 4, 2019
Priority date	Nov 26, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A digital-to-analog converter (DAC) is described having a digital input, an analogue output, and two capacitors. The DAC has a controller. The controller is configured to generate a switching sequence including at least two switch cycles dependent on the input value received on the digital input. If the input value corresponds to an odd number, in a first switch cycle during a switch cycle first phase, the controller switchably couples a reference voltage to a first terminal and a ground voltage to a second terminal of one of the two capacitors, and switchably couples a ground voltage to a first terminal and the reference voltage to a second terminal of the other of the two capacitors. During a switch cycle second phase, the controller switchably couples a ground voltage to the first terminal and the analogue output to the second terminal of both capacitors.

First claim

The invention claimed is:

1. A digital-to-analog converter comprising:
a digital input; an analogue output; two capacitors, each capacitor having a first terminal and a second terminal; and
a controller coupled to the digital input and a clock input, wherein the controller is configured to generate a switching sequence comprising at least two switch cycles dependent on the input value received on the digital input and wherein if the input value corresponds to an odd number, the controller is configured to in a first switch cycle:
during a switch cycle first phase:
switchably couple a reference voltage to a first terminal and a ground voltage to a second terminal of one of the two capacitors, and switchably couple a ground voltage to a first terminal and the reference voltage to a second terminal of the other of the two capacitors, and

during a switch cycle second phase:
switchably couple a ground voltage to the first terminal and the analogue output to the second terminal of both capacitors.

2. The digital-to-analog converter of claim 1 wherein the switching sequence further comprises a logic-one switch cycle wherein the controller is further configured to
during a switch cycle first phase:
switchably couple a reference voltage to a first terminal and a ground voltage to a second terminal of one of the two capacitors, and switchably couple a ground voltage to a second terminal of the other of the two capacitors, and

during a switch cycle second phase:
switchably couple a ground voltage to the first terminal and the analogue output to the second terminal of both capacitors.

3. The digital-to-analog converter of claim 1 wherein the switching sequence further comprises a logic-zero switch cycle wherein the controller is further configured to:
during a switch cycle first phase:
switchably couple a ground voltage to a first terminal and a ground voltage to a second terminal of one of the two capacitors, and switchably couple a ground voltage to a second terminal of the other of the two capacitors.

4. The digital-to-analog converter of claim 1 wherein the switching sequence further comprises a logic-minus-one switch cycle wherein the controller is further configured to:
during a switch cycle first phase:
switchably couple a ground voltage to a first terminal and a reference voltage to a second terminal of one of the two capacitors, and switchably couple a ground voltage to a second terminal of the other of the two capacitors.

5. The digital-to-analog converter of claim 1 wherein the controller is configured to generate a logic-minus-one switch cycle followed by a logic-one switch cycle in response to the input value comprising a logic one followed by a logic zero.

6. The digital-to-analog converter of claim 1 wherein the controller is configured to generate at least one logic-one switch cycle dependent on the input value.

7. The digital-to-analog converter of claim 1 wherein the controller is configured to generate at least one logic-zero switch cycle dependent on the input value.

8. The digital-to-analog converter of claim 1 wherein the controller is configured during a switch cycle second phase to:
switchably couple a ground voltage to the first terminal and the analogue output to the second terminal of both capacitors.

9. The digital-to-analog converter of claim 1 wherein the controller is configured during a switch cycle second phase to:
switchably couple a reference voltage to the second terminal and the analogue output to the first terminal of both capacitors.

10. The digital-to-analog converter of claim 1 comprising a switch network coupled to each terminal of the two capacitors wherein in the switch terminal is configured to switchably couple one of a ground terminal, a voltage reference terminal, and the analog output, to each capacitor terminal, wherein the controller comprises a control output coupled to the switch network.

11. The digital-to-analog converter of claim 1 wherein the number of switch sequences is even.

12. The digital-to-analog converter of claim 1 wherein the switching sequence comprises N switch cycles for N-bit resolution if N is even and N+1 switch cycles if N is odd.

13. The digital to analog converter of claim 1 wherein the controller comprises a clock input configured to receive a clock and wherein each switch cycle corresponds to one clock period.

14. A successive approximation analog-to-digital converter comprising the digital to analog converter of claim 1 .

15. A method of digital to analog conversion for a digital-to-analog converter comprising: a digital input; an analogue output; and two capacitors, each capacitor having a first terminal and a second terminal, the method comprising
generating a switching sequence comprising a number of switch cycles dependent on the input value received on the digital input and wherein if the input value corresponds to an odd number, in a first switch cycle:
during a switch cycle first phase:
switchably coupling a reference voltage to a first terminal and a ground voltage to a second terminal of one of the two capacitors, and switchably coupling a ground voltage to a first terminal and the reference voltage to a second terminal of the other of the two capacitors, and
during a switch cycle second phase:
switchably coupling a ground voltage to the first terminal and the analogue output to the second terminal of both capacitors.

Assignees

• Nxp Bv

Inventors

• Albinet Xavier

Classifications

• H03M1/667 Primary

  Recirculation type · CPC title

• H03M1/0665 Primary

  using data dependent selection of the elements, e.g. data weighted averaging · CPC title

• H03M1/466

  using switched capacitors · CPC title