Stochastic time-to-digital converter and operating method thereof

Patent metadata

Field	Value
Publication number	US-10840928-B2
Application number	US-201916689246-A
Country	US
Kind code	B2
Filing date	Nov 20, 2019
Priority date	Nov 21, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

Disclosed is a stochastic time-to-digital converter, which includes a first arbiter cell that compares a timing of a reference signal and a timing of an input signal based on a voltage selected by a first selection signal from among a first voltage or a second voltage and outputs a first comparison result, a second arbiter cell that compares the timing of the reference signal with the timing of the input signal based on a voltage selected by a second selection signal from among the first voltage or the second voltage and outputs a second comparison result, and a binary converter that calculates a phase difference between the reference signal and the input signal based on the first comparison result and the second comparison result.

First claim

What is claimed is:

1. A stochastic time-to-digital converter comprising:
a first arbiter cell configured to compare a timing of a reference signal with a timing of an input signal based on a voltage selected by a first selection signal from among a first voltage or a second voltage and to output a first comparison result;
a second arbiter cell configured to compare the timing of the reference signal with the timing of the input signal based on a voltage selected by a second selection signal from among the first voltage or the second voltage and to output a second comparison result; and
a binary converter configured to calculate a phase difference between the reference signal and the input signal based on the first comparison result and the second comparison result.

2. The stochastic time-to-digital converter of claim 1 , wherein each of the first selection signal and the second selection signal is a 1-bit signal.

3. The stochastic time-to-digital converter of claim 1 , wherein, when the first arbiter cell operates based on the first voltage, the first arbiter cell has a first time offset, and
wherein, when the first arbiter cell operates based on the second voltage, the first arbiter cell has a second time offset different from the first time offset.

4. The stochastic time-to-digital converter of claim 3 , wherein, when the second arbiter cell operates based on the first voltage, the second arbiter cell has a third time offset different from the first time offset, and
wherein, when the second arbiter cell operates based on the second voltage, the second arbiter cell has a fourth time offset different from the second time offset.

5. The stochastic time-to-digital converter of claim 1 , wherein the first selection signal and the second selection signal are determined so that an integral non-linearity (INL) error of the stochastic time-to-digital converter is minimized.

6. The stochastic time-to-digital converter of claim 1 , wherein the first selection signal and the second selection signal are determined based on a process corner characteristic of the stochastic time-to-digital converter.

7. The stochastic time-to-digital converter of claim 1 , further comprising:
a scan-chain circuit configured to receive the first selection signal and the second selection signal in series through one pad in response to a first clock signal and to respectively provide the first selection signal and the second selection signal to the first arbiter cell and the second arbiter cell in parallel in response to a second clock signal.

8. An operating method of a stochastic time-to-digital converter which includes a plurality of arbiter cells, the method comprising:
receiving selection signals corresponding to at least two arbiter cells of the plurality of arbiter cells;
generating a timing comparison result of comparing a timing of a reference signal with a timing of an input signal, based on a voltage selected by a corresponding selection signal of the selection signals from among a first voltage or a second voltage, through each of the at least two arbiter cells; and
calculating a phase difference between the reference signal and the input signal based on timing comparison results of the reference signal and the input signal generated from the at least two arbiter cells.

9. The method of claim 8 , wherein each of the selection signals is a 1-bit signal.

10. The method of claim 8 , wherein each of the at least two arbiter cells has different time offsets with respect to the first voltage and the second voltage.

11. The method of claim 8 , wherein the selection signals are determined so that an integral non-linearity (INL) error of the stochastic time-to-digital converter is minimized.

12. The method of claim 8 , wherein the selection signals are determined based on a process corner characteristic of the stochastic time-to-digital converter.

13. The method of claim 8 , wherein a time offset which each of the at least two arbiter cells has with respect to the selected voltage is within an input range of the stochastic time-to-digital converter.

14. The method of claim 8 , wherein, when a number of the at least two arbiter cells is “m”, a number of combinations of time offsets which the at least two arbiter cells have is 2 m .

Assignees

• Univ Korea Res & Business Foundation Sejong Campus
• Univ Korea Res & Bus Found

Inventors

• Chung Hayun Cecillia

Classifications

• H03M1/04 Primary

  using stochastic techniques · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title