Synchronous buck inverter

Patent metadata

Field	Value
Publication number	US-10840824-B2
Application number	US-201715724839-A
Country	US
Kind code	B2
Filing date	Oct 4, 2017
Priority date	Sep 8, 2014
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A power inverter, such as a synchronous buck power inverter, that is configured with a high frequency switching control having a (PWM) controller and sensing circuit. Controller provides a low frequency oscillating wave to effect switching control on a synchronous-buck circuit portion that includes a plurality of switches to invert every half cycle of the frequency provided by controller. The inverting process thus creates a positive and negative transition of the oscillating wave signal. A low frequency switching stage includes a further plurality of switches configured to operate as zero voltage switching (ZVS) and zero current switching (ZCS) drives Charge on an output capacitor is discharged to zero on every zero crossing of low frequency switching stage and advantageously discharges energy every half cycle. During this discharge of energy, the zero crossing distortion in the low frequency sine wave is greatly reduced.

First claim

What is claimed is:

1. A power inverter, comprising:
an input for receiving DC power;
an output for providing AC power to a load;
a high frequency switching control circuit, operatively coupled to the input;
a synchronous-buck circuit, operatively coupled to the high frequency switching control circuit and the output, the synchronous buck circuit comprising a plurality of switches and configured to invert every half cycle of the signal provided by the high frequency switching control circuit; and
a low frequency switching circuit, operatively coupled to at least the synchronous buck circuit and the output to provide zero voltage switching and zero current switching by driving an output capacitor to discharge on each zero crossing of the low frequency switching circuit.

2. The power inverter according to claim 1 , wherein the high frequency switching control circuit comprises a controller and a sensing circuit.

3. The power inverter according to claim 2 , wherein the controller comprises a current-mode PWM controller.

4. The power inverter according to claim 2 , wherein the sensing circuit comprises at least one of a peak current sense and an output voltage sense.

5. The power inverter according to claim 1 , wherein the plurality of switches for the synchronous-buck circuit comprise field effect transistors (FETs).

6. The power inverter according to claim 1 , wherein the high frequency switching control circuit is configured to provide a low frequency sine wave to effect switching control on the synchronous-buck circuit.

7. The power inverter according to claim 1 , wherein the synchronous buck circuit comprises a plurality of drive circuits, each operatively coupled to a respective one of the plurality of switches.

8. The power inverter according to claim 1 , wherein one of the plurality of switches for the synchronous-buck circuit is configured to be active on a high frequency PWM for a positive half wave of the high frequency switching control circuit, and another of the plurality of switches for the synchronous-buck circuit is active on a high frequency PWM complement for the positive half wave of the high frequency switching control circuit.

9. The power inverter according to claim 1 , wherein one of the plurality of switches for the synchronous-buck circuit is configured to be active on a high frequency PWM for a negative half wave of the high frequency switching control circuit, and another of the plurality of switches for the synchronous-buck circuit is active on a high frequency PWM complement for the negative half wave of the high frequency switching control circuit.

10. The power inverter according to claim 1 , further comprising a dither circuit operatively coupled to the high frequency switching control circuit, wherein the dither circuit is configured to cause a frequency change in the switching control circuit.

11. The power inverter according to claim 10 , wherein the dithering circuit is configured to apply a waveform to the high frequency switching control circuit to cause the frequency change.

12. The power inverter according to claim 11 , wherein the dithering circuit is configured to apply a triangular waveform to the high frequency switching control circuit to cause the frequency change.

13. The power inverter according to claim 10 , wherein the dither circuit is configured to cause the frequency change in the switching control circuit by reducing a switching frequency at a zero crossing.

14. The power inverter according to claim 1 , wherein each of the plurality of switches for the synchronous buck circuit comprises one of Silicon Carbide switches and Gallium Nitride switches.

15. A power inverter, comprising:
an input for receiving DC power;
an output for providing AC power to a load;
a high frequency switching control circuit, operatively coupled to the input;
a synchronous-buck circuit, operatively coupled to the high frequency switching control circuit and the output;
a low frequency switching circuit, operatively coupled to the synchronous buck circuit and the output; and
a capacitive circuit comprising a discharge capacitor, the capacitive circuit operatively coupled to the output, the low frequency switching circuit and the synchronous buck circuit, the capacitive circuit being configured to discharge the discharge capacitor to zero on at least one zero crossing of the low frequency switching circuit.

16. The power inverter according to claim 15 , wherein a plurality of switches for the low frequency switching circuit comprise field effect transistors (FETs).

17. The power inverter according to claim 15 , wherein the high frequency switching control circuit is configured to provide a low frequency sine wave to effect switching control on the synchronous-buck circuit.

18. The power inverter according to claim 15 , wherein the synchronous buck circuit comprises a plurality of drive circuits.

19. The power inverter according to claim 15 , wherein the low frequency switching circuit comprises a plurality of drive circuits.

20. The power inverter according to claim 15 , wherein one aspect of the low frequency switching circuit is configured to be on for a positive half wave of the high frequency switching control circuit, and another aspect of the low frequency switching circuit is off for the positive half wave of the low frequency switching circuit.

Assignees

• Jabil Inc

Inventors

• Beebe Ronald
• Compton Christopher D
• Eckerson David
• Liu Yizhe
• Talebi Salman

Classifications

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title

• H02M1/0058

  by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero (using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826) · CPC title

• H03B5/26

  frequency-determining element being part of bridge circuit in closed ring around which signal is transmitted; frequency-determining element being connected via a bridge circuit to such a closed ring, e.g. Wien-Bridge oscillator, parallel-T oscillator · CPC title