Nanowire transistors with embedded dielectric spacers

Patent metadata

Field	Value
Publication number	US-10840352-B2
Application number	US-201515780619-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Dec 22, 2015
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

Nanowire transistors including embedded dielectric spacers to separate a gate electrode from source and drain regions of the transistor. Embedded spacers are disposed within interior sidewalls of a passage through which the gate electrode wraps around a semiconductor filament. The presence of these embedded spacers may dramatically reduce fringe capacitance, particularly as the number of wires/ribbons/filaments in the transistor increases and the number of interior gate electrode passages increases. In some advantageous embodiments, embedded dielectric spacers are fabricated by encapsulating external surfaces prior to those surfaces becoming embedded within the transistor.

First claim

What is claimed is:

1. A transistor structure, comprising:
a filament comprising a semiconductor, the filament extending a first lateral length between a source and a drain;
a gate stack between an underlying substrate and the filament within a channel portion of the first lateral length, the gate stack comprising a gate electrode material separated from the filament by a gate dielectric material; and
an embedded spacer comprising a dielectric material, the embedded spacer between the filament and the substrate within an end portion of the first lateral length, and the embedded spacer separating the gate stack from the source or the drain, wherein:
the filament is over a region of the substrate comprising a crystalline semiconductor that is surrounded by an isolation dielectric region of the substrate;
the source and the drain each comprise doped semiconductor crystals in contact with the crystalline semiconductor region of the substrate; and
an interface between the crystalline semiconductor region of the substrate and the source and drain crystals is below the top surface of the isolation dielectric region by an amount substantially equal to the end portion of the first lateral length.

2. The transistor structure of claim 1 , wherein the filament is a first filament and the transistor further comprises a second filament over the first filament, and extending the first lateral length between the source and the drain, and wherein:
the gate stack is between the first and second filaments with the gate dielectric separating the gate electrode material from the first and second filaments; and
the embedded spacer is between the first and second filaments, within the end portion of the first lateral length.

3. The transistor structure of claim 1 , wherein the embedded spacer comprises an amorphous dielectric material having a bulk relative permittivity below 3.5.

4. The transistor structure of claim 1 , wherein:
the gate stack is over a top surface of the filament, opposite the substrate, and extends a second lateral length beyond the filament in a direction orthogonal to the first lateral length; and
the transistor structure further comprises an external spacer comprising a dielectric material, wherein the external spacer extends the second lateral length and is adjacent to a sidewall of the filament separating the gate electrode material from the source or the drain.

5. The transistor structure of claim 4 , wherein:
the external spacer contacts a sidewall of the embedded spacer;
the gate dielectric material contacts a sidewall of the embedded spacer; and
the source or drain contacts a sidewall of the embedded spacer.

6. The transistor structure of claim 5 , wherein: the external spacer separates the gate electrode material from the source and the drain by a distance substantially equal to a distance by which the embedded spacer separates the gate electrode material from the source and drain.

7. The transistor structure of claim 6 , wherein:
the end portion comprises less than 4 nm of the first lateral length; and
the external spacer separates the gate stack from the source and the drain by no more than 4 nm.

8. The transistor structure of claim 5 , wherein the external spacer comprises an amorphous dielectric material having a first composition, and the embedded spacer comprises an amorphous dielectric material having a second composition, different than the first composition.

9. The transistor structure of claim 8 , wherein the embedded spacer comprises a dielectric material having a lower relative permittivity than that of the external spacer.

10. The transistor structure of claim 1 , wherein:
the filament is a crystal of Ge or a III-V compound;
the source and drain each comprise an impurity-doped crystal of Ge or a III-V compound;
the gate dielectric material comprises oxygen and at least one of Hf, Al, or Ta; and
the gate electrode material comprises one or more metal.

11. The transistor structure of claim 10 , wherein:
the filament comprises a crystal of Ge; and
the source and drain are both doped with acceptor impurities.

12. A microprocessor, comprising a plurality of nanowire transistors, each nanowire transistor having the transistor structure of claim 1 .

13. The microprocessor of claim 12 , wherein:
the filaments in at least a subset of the nanowire transistors comprise a crystal of predominantly Ge; and
the source and drain also comprise predominantly Ge and are doped with acceptor impurities.

14. A method of fabricating a nanowire transistor, the method comprising:
forming a fin comprising a non-sacrificial semiconductor material layer, and a sacrificial material layer between the non-sacrificial semiconductor material layer and an underlying substrate, wherein forming the fin further comprises:
forming a mask over the fin protecting a first lateral length of the non-sacrificial semiconductor material; and
removing unmasked portions of the fin by etching both the sacrificial and non-sacrificial material layers to expose a crystalline semiconductor region of the substrate adjacent to an isolation dielectric material;

forming lateral recesses between the non-sacrificial semiconductor material layer and the substrate by partially etching the sacrificial material layer at opposite ends of the fin, wherein partially etching the sacrificial material layer also recesses an exposed surface of the crystalline semiconductor region of the substrate to a depth below a surface of the isolation dielectric material that is substantially equal to a width of the lateral recesses;
embedding a dielectric material within the lateral recesses by depositing an amorphous material over the mask and over ends of the fin protected by the mask, the amorphous material at least partially backfilling the lateral recesses;
removing the amorphous material from the crystalline semiconductor region of the substrate while retaining the dielectric material embedded within the lateral recesses;
epitaxially growing a source crystal and a drain crystal from the crystalline semiconductor region of the substrate, the source and drain crystals contacting end portions of the non-sacrificial semiconductor material layer; and
replacing a remaining portion of the sacrificial material layer between the ends of the fin with a gate stack comprising a gate electrode material separated from the non-sacrificial semiconductor material layer by a gate dielectric material, and spaced apart from the source and drain crystals by the dielectric material embedded within the lateral recesses.

15. The method of claim 14 , wherein
replacing a remaining portion of the sacrificial material layer with the gate stack further comprises:
removing at least a portion of the mask to expose a channel portion of the non-sacrificial material layer between the end portions;
removing the sacrificial material layer between the non-sacrificial material layer and the substrate material within the channel portion to form a filament comprising semiconductor material;
depositing the gate dielectric material on all exposed surfaces of the filament and on a surface of the dielectric material; and
depositing the gate electrode material on the gate dielectric material in a space between the filament and the substrate.

16. The method of claim 14 , wherein:
depositing the amorphous material over the mask further comprises conformally depositing a dielectric material having a relative permittivity below 3.5; and
removing the dielectric material from sidewalls of the mask while retaining the dielectric material embedde

Assignees

• Intel Corp

Inventors

• Rachmady Willy
• Sung Seung Hoon
• Kavalieros Jack T
• Gardner Sanaz K

Classifications

• H10D62/852

  being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP · CPC title

• H10D62/402

  Amorphous materials · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title