Enhancement mode high electron mobility transistor (HEMT)

Patent metadata

Field	Value
Publication number	US-10840348-B2
Application number	US-201816114650-A
Country	US
Kind code	B2
Filing date	Aug 28, 2018
Priority date	Aug 29, 2017
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlxTi1-xO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlxTi1-xO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlxTi1-xO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, Ron=8.9 Ωmm, interface trap density <1010 mm−2eV−1 and gate leakage below 200 nA/mm at the OFF-state breakdown.

First claim

We claim:

1. A transistor comprising:
a source;
a drain; and
a hybrid gate stack that comprises Al x Ti 1-x O that is an oxide that demonstrates p-type behaviour, wherein said Al x Ti 1-x O demonstrates p-type behaviour by positioning a conduction band above a fermi level in a channel region, that is used as a control parameter to deplete two dimensional electron gas (2DEG) in the channel; and
wherein said hybrid gate stack is supported by an AlGaN/GaN stack, and wherein the hybrid gate stack is brought closer to a channel by partial removal of an AlGaN barrier under said hybrid gate stack, followed by deposition of said Al x Ti 1-x O.

2. The transistor as claimed in 1 , wherein said Al x Ti 1-x O is formed by Al doping of TiO 2 so as to impact said p-type behaviour to said oxide.

3. The transistor as claimed in claim 1 , wherein said transistor is a High Electron Mobility Transistor (HEMT).

4. The transistor as claimed in claim 1 , wherein Al content in said oxide is a controlling parameter for a threshold voltage.

5. The transistor as claimed in claim 1 , wherein the hybrid gate stack further comprises a p-type GaN cap.

6. The transistor as claimed in claim 1 , wherein said transistor is operated in an enhancement mode.

7. A transistor comprising:
a source;
a drain; and
a hybrid gate stack that comprises one or more p-type metal oxides, wherein the one or more p-type metal oxides demonstrate p-type behaviour by positioning a conduction band above a fermi level in a channel region; and
wherein the hybrid gate stack is supported by an AlGaN/GaN stack, and wherein the hybrid gate stack is brought closer to a channel by partial removal of an AlGaN barrier under said hybrid gate stack, followed by deposition of said p-type metal oxide.

8. The transistor as claimed in claim 7 , wherein the hybrid gate stack further comprises a p-type GaN cap.

9. The transistor as claimed in claim 7 , wherein the hybrid gate stack further comprises an insulator or dielectric material.

10. A method of making an Al x Ti 1-x O based dielectric that demonstrates p-type behaviour, said method comprising the steps of using atomic layer deposition (ALD) to enable deposition of Al 2 O 3 and TiO 2 across a plurality of cycles to introduce Al atoms in TiO 2 , wherein said Al x Ti 1-x O demonstrates p-type behaviour by positioning a conduction band above a fermi level in a channel region, that is use as a control parameter to deplete two dimensional electron gas (2DEG) in the channel; and
wherein the Al x Ti 1-x O based dielectric is associated with a high electron mobility transistor.

11. The method of claim 10 , wherein the method further comprises the step of depositing Al 2 O 3 in an ALD chamber using cycles involving introduction of trimethylaluminium (TMA) and H 2 O precursors.

12. The method of claim 10 , wherein the method further comprises the step of depositing TiO 2 in said ALD chamber using cycles involving introduction of Titanium tetraisopropoxide (TTIP) and H 2 O precursors.

Assignees

• Indian Inst Scient

Inventors

• Shrivastava Mayank
• Dutta Gupta Sayak
• Soni Ankit
• Raghavan Srinivasan
• Bhat Navakanta

Classifications

• H10P14/69397

  the material containing two or more metal elements · CPC title

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6339 Primary

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title