Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10840269-B2
Application number	US-201716066696-A
Country	US
Kind code	B2
Filing date	Mar 29, 2017
Priority date	Mar 29, 2017
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A semiconductor device provided in a pixel circuit of a display device includes, in order from a lower side: a substrate; an LTPS layer; a first gate insulating layer; a first metal layer; a first flattened layer; a second gate insulating layer; an oxide semiconductor layer; a second metal layer; a passivation layer; and a third metal layer. The gate electrode layer of an LTPS-TFT and the gate electrode of an oxide semiconductor TFT are formed by the first metal layer.

First claim

The invention claimed is:

1. A semiconductor device provided in a pixel circuit of a display device, the semiconductor device comprising, in order from a lower side:
a substrate;
a semiconductor layer of a first transistor;
a first insulating layer;
a first metal layer;
a single first flattened layer;
a second insulating layer;
a semiconductor layer of a second transistor;
a second metal layer;
a third insulating layer; and
a third metal layer, wherein
the first transistor includes low-temperature polysilicon as a semiconductor material,
the second transistor includes an oxide semiconductor as a semiconductor material,
a gate electrode of the first transistor and a gate electrode of the second transistor are defined by the first metal layer,
the first insulating layer, the second insulating layer, and the third insulating layer are made from an inorganic material,
the single first flattened layer consists of a Spin on Glass (SOG) material, and
in the second transistor:
an opening is provided in the single first flattened layer,
the opening exposes at least a portion of the first metal layer,
the at least a portion of the first metal layer exposed by the opening is covered by the second insulating layer, and

the semiconductor layer of the second transistor and the second metal layer are located in a portion of the opening, and
the single first flattened layer directly contacts a top surface of the gate electrode of the second transistor.

2. The semiconductor device according to claim 1 , wherein a source electrode and a drain electrode of the first transistor are electrically connected to the third metal layer through a contact hole in the first insulating layer, a contact hole in the single first flattened layer, a contact hole in the second insulating layer, and a contact hole in the third insulating layer located between the source electrode and the drain electrode and the third metal layer.

3. The semiconductor device according to claim 2 , wherein when viewed from a direction perpendicular to the substrate:
circumferential ends of the contact hole in the first insulating layer and the contact hole in the first flattened layer coincide,
circumferential ends of the contact hole in the second insulating layer and the contact hole in the third insulating layer coincide,
an opening of the contact hole in the first insulating layer is narrower than an opening of the contact hole in the second insulating layer, and
a circumference of the contact hole is consistent throughout each of the first insulating layer, the single first flattened layer, the second insulating layer, and the third insulating layer.

4. The semiconductor device according to claim 1 , wherein the second transistor is a driving transistor that drives a light emitting element provided in the pixel circuit.

5. The semiconductor device according to claim 1 , wherein the second transistor further includes a second gate electrode including the third metal layer.

6. The semiconductor device according to claim 5 , wherein of the semiconductor layer of the second transistor, the semiconductor layer is located above the single first flattened layer, all portions of the semiconductor layer located between a source electrode and a drain electrode of the second transistor overlap with the second gate electrode, with the third insulating layer being located between the semiconductor layer and the second gate electrode, and the semiconductor layer is in contact with an end portion of the source electrode of the second transistor and an end portion of the drain electrode of the second transistor.

7. The semiconductor device according to claim 1 , wherein
the gate electrode of the first transistor and the gate electrode of the second transistor are the same,
a source electrode of the first transistor is electrically connected to a source electrode of the second transistor, and
a drain electrode of the first transistor is electrically connected to a drain electrode of the second transistor.

Assignees

• Sharp Kk

Inventors

• Okabe Tohru
• Tanaka Tetsunori
• Yaneda Takeshi

Classifications

• H10D30/0312

  characterised by the gate electrodes · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title

• H10D30/6732

  Bottom-gate only TFTs · CPC title