Chip resistor manufacturing method, and chip resistor

Patent metadata

Field	Value
Publication number	US-10839990-B2
Application number	US-201816341094-A
Country	US
Kind code	B2
Filing date	Jan 17, 2018
Priority date	Feb 8, 2017
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A chip resistor having a predetermined resistance value is manufactured by the following method. A resistive element is provided on an upper surface of an insulating substrate. The resistive element includes a wide portion, a first narrow portion extending from the wide portion, and a part extending from the wide portion, the first narrow portion has a smaller width than the wide portion. First and second electrodes are provided on the upper surface of the insulating substrate. The first electrode is located away from the wide portion. The first electrode contacts the first narrow portion. The first electrode overlaps the first narrow portion when viewed from above. The second electrode contacts the part of the resistive element. The second electrode overlaps the part of the resistive element when viewed from above. A distance between the narrow portion and the wide portion is determined so as to cause a resistance value between the first and second electrodes to be the predetermined resistance value. This method improves the precision of the resistance value of the chip resistor.

First claim

The invention claimed is:

1. A method of manufacturing a chip resistor having a predetermined resistance value, the method comprising:
providing a resistive element on an upper surface of an insulating substrate, the resistive element including a wide portion, a first narrow portion extending from the wide portion, and a part extending from the wide portion, the first narrow portion having a smaller width than the wide portion;
providing a first electrode on a first end portion of the upper surface of the insulating substrate, the first electrode being located away from the wide portion by a first distance, the first electrode contacting the first narrow portion, the first electrode overlapping the first narrow portion when viewed from above;
providing a second electrode on a second end portion of the upper surface of the insulating substrate, the second electrode contacting the part of the resistive element, the second electrode overlapping the part of the resistive element when viewed from above; and
determining the first distance so as to cause a resistance value between the first electrode and the second electrode to be the predetermined resistance value,
wherein said providing the first electrode comprises:
providing a first electrode layer located away from the wide portion by a second distance larger than the first distance, the first electrode layer contacting the first narrow portion, the first electrode layer overlapping the first narrow portion when viewed from above; and
providing a second electrode layer located away from the wide portion by the first distance, the second electrode layer contacting the first narrow portion and the first electrode layer, the second electrode layer overlapping the first narrow portion and the first electrode layer when viewed from above.

2. The method of claim 1 , further comprising:
adjusting the resistance value by forming a trimming groove in the wide portion.

3. The method of claim 2 ,
wherein the wide portion, the first narrow portion, and the part are arranged in a predetermined direction such that the wide portion is positioned between the first narrow portion and the part of the resistive element, and
wherein said adjusting the resistance value comprises adjusting the resistance value by forming the trimming groove in the wide portion such that the trimming groove overlaps none of the first narrow portion and the part of the resistive element when viewed in the predetermined direction.

4. A method of manufacturing a chip resistor having a predetermined resistance value, the method comprising:
providing a resistive element on an upper surface of an insulating substrate, the resistive element including a wide portion, a first narrow portion extending from the wide portion, and a part extending from the wide portion, the first narrow portion having a smaller width than the wide portion;
providing a first electrode on a first end portion of the upper surface of the insulating substrate, the first electrode being located away from the wide portion by a first distance, the first electrode contacting the first narrow portion, the first electrode overlapping the first narrow portion when viewed from above;
providing a second electrode on a second end portion of the upper surface of the insulating substrate, the second electrode contacting the part of the resistive element, the second electrode overlapping the part of the resistive element when viewed from above; and
determining the first distance so as to cause a resistance value between the first electrode and the second electrode to be the predetermined resistance value,
wherein the part of the resistive element is a second narrow portion extending from the wide portion and having a smaller width than the wide portion,
wherein said providing the second electrode on the second end portion of the upper surface of the insulating substrate comprises providing the second electrode on the second end portion of the upper surface of the insulating substrate such that the second electrode is located away from the wide portion by a second distance, the second electrode contacts the second narrow portion, and the second electrode overlaps the second narrow portion when viewed from above,
wherein said determining the first distance so as to cause the resistance value between the first electrode and the second electrode to be the predetermined resistance value comprises determining the first distance and the second distance so as to cause the resistance value between the first electrode and the second electrode to be the predetermined resistance value,
wherein said providing the first electrode comprises:
providing a first electrode layer located away from the wide portion by a third distance larger than the first distance, the first electrode layer contacting first narrow portion, the first electrode layer overlapping the first narrow portion when viewed from above; and
providing a second electrode layer located away from the wide portion by the first distance, the second electrode layer contacting the first narrow portion and the first electrode layer, the second electrode layer overlapping the first narrow portion and the first electrode layer when viewed from above, and

wherein said providing the second electrode comprises:
providing a third electrode layer located away from the wide portion by a fourth distance larger than the second distance, the third electrode layer contacting the second narrow portion, the third electrode layer overlapping the second narrow portion when viewed from above; and
providing a fourth electrode layer located away from the wide portion by the second distance, the fourth electrode layer contacting the second narrow portion and the third electrode layer, the fourth electrode layer overlapping the second narrow portion and the third electrode layer when viewed from above.

5. The method of claim 4 , further comprising:
adjusting the resistance value by forming a trimming groove in the wide portion.

6. The method of claim 5 ,
wherein the wide portion, the first narrow portion, and the second narrow portion are arranged in a predetermined direction such that the wide portion is positioned between the first narrow portion and the second narrow portion, and
wherein said adjusting the resistance value comprises adjusting the resistance value by forming the trimming groove in the wide portion such that the trimming groove overlaps none of the first narrow portion and the second narrow portion when viewed in the predetermined direction.

7. A chip resistor comprising:
an insulating substrate;
a first electrode provided on a first end portion of an upper surface of the insulating substrate;
a second electrode provided on a second end portion of the upper surface of the insulating substrate;
a resistive element provided on the upper surface of the insulating substrate and connected to the first electrode and the second electrode, the resistive element overlapping the first electrode and the second electrode;
a third electrode covering the first electrode; and
a fourth electrode covering the second electrode,
wherein the resistive element includes a wide portion, a first narrow portion extending from the wide portion, and a part extending from the wide portion, the wide portion having a trimming groove provided therein, a width of a first narrow portion being smaller than a width of the wide portion,
wherein the first electrode is connected to the first narrow portion of the resistive element, is located away from the wide portion by a first distance, and overlaps the first narrow portion of the resistive element,
wherein the second electrode is connected to the part of the resistive element and overlaps the part of the resistive ele

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Yamada Koichi
• Nakayama Shogo

Classifications

• H01C17/281 Primary

  by thick film techniques · CPC title

• H01C17/24

  by removing or adding resistive material (H01C17/23, H01C17/232, H01C17/235 take precedence) · CPC title

• H01C7/003

  Thick film resistors · CPC title

• H01C17/065

  by thick film techniques, e.g. serigraphy · CPC title

• H01C1/142 Primary

  the terminals or tapping points being coated on the resistive element · CPC title