SLA-based power management in disaggregated computing systems

Patent metadata

Field	Value
Publication number	US-10838482-B2
Application number	US-201615289274-A
Country	US
Kind code	B2
Filing date	Oct 10, 2016
Priority date	Oct 10, 2016
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

For power management in a disaggregated computing system, initial electrical power levels are distributed thereby allocating a voltage and a clock speed to each one of a set of processor cores in the disaggregated computing system. The voltage and the clock speed of respective processor cores within the set of processor cores are adjusted according to a workload priority of respective workloads performed by each respective one of the processor cores, wherein the workload priority is assigned based upon a service level agreement (SLA).

First claim

What is claimed is:

1. A method for power management in a disaggregated computing system, by a processor device, comprising:
dynamically constructing the disaggregated computing system using individual hardware components selected from a plurality of component pools; wherein the disaggregated computing system is assembled as a non-virtualized bare-metal computing system having connections formed between the individual hardware components using optical links;
distributing initial electrical power levels thereby allocating a voltage and a clock speed to each one of a set of processor cores in the disaggregated computing system; wherein the initial electrical power levels aggregate to an initial collective power level, the initial collective power level comprising a total electrical power allocation contracted from an electrical utility;
adjusting the voltage and the clock speed of respective processor cores within the set of processor cores according to a workload priority of respective workloads performed by each respective one of the processor cores, wherein the workload priority is assigned based upon a service level agreement (SLA); wherein the voltage and the clock speed of the respective processor cores is individually adjusted irrespective of a location of the respective processor cores within the plurality of component pools; and
coincident with adjusting the voltage and the clock speed of the respective processor cores, balancing the voltage and clock speed between each one of the set of processor cores such that an aggregate electrical capacity is produced to execute a collective demanded workload of the respective workloads while maintaining an approximately constant electrical power level within a threshold of the initial collective power level.

2. The method of claim 1 , wherein the workload priority is selected from a plurality of priority levels including at least a low priority level, a medium priority level, and a high priority level; and
each one of the plurality of priority levels include an allocated range having a floor and a ceiling of the voltage and the clock speed adjusted therebetween.

3. The method of claim 2 , further including performing:
statically defining, for each one of the plurality of priority levels, the range of the voltage and the clock speed allocated therein; or
automatically estimating, for each one of the plurality of priority levels, the range of the voltage and the clock speed allocated therein by analyzing a historical usage data of the respective workloads.

4. The method of claim 3 , further including analyzing the historical usage data of the respective workloads to categorize the respective workloads into one of the plurality of priority levels; and
building workload groups comprising multiple ones of the respective workloads having a same workload priority based upon the SLA of the respective workloads; wherein the workload groups are generated on a ranked list.

5. The method of claim 2 , further including re-allocating thereby re-adjusting the voltage and the clock speed of one of the respective processor cores performing the respective workloads having a lower one of the plurality of priority levels to another one of the respective processor cores performing the respective workloads having a higher one of the plurality of priority levels.

6. The method of claim 5 , further including, upon detection of a reduction of an input capacity able to produce the initial collective power level, maintaining the allocated voltage and clock speed of the respective processor cores performing the respective workloads having the higher one of the plurality of priority levels while reducing the allocated voltage and clock speed of the respective processor cores performing the respective workloads having the lower one of the plurality of priority levels.

7. A system for power management in a disaggregated computing system, the system comprising:
at least one processor device, wherein the at least one processor device:
dynamically constructs the disaggregated computing system using individual hardware components selected from a plurality of component pools; wherein the disaggregated computing system is assembled as a non-virtualized bare-metal computing system having connections formed between the individual hardware components using optical links;
distributes initial electrical power levels thereby allocating a voltage and a clock speed to each one of a set of processor cores in the disaggregated computing system; wherein the initial electrical power levels aggregate to an initial collective power level, the initial collective power level comprising a total electrical power allocation contracted from an electrical utility;
adjusts the voltage and the clock speed of respective processor cores within the set of processor cores according to a workload priority of respective workloads performed by each respective one of the processor cores, wherein the workload priority is assigned based upon a service level agreement (SLA); wherein the voltage and the clock speed of the respective processor cores is individually adjusted irrespective of a location of the respective processor cores within the plurality of component pools; and
coincident with adjusting the voltage and the clock speed of the respective processor cores, balances the voltage and clock speed between each one of the set of processor cores such that an aggregate electrical capacity is produced to execute a collective demanded workload of the respective workloads while maintaining an approximately constant electrical power level within a threshold of the initial collective power level.

8. The system of claim 7 , wherein the workload priority is selected from a plurality of priority levels including at least a low priority level, a medium priority level, and a high priority level; and
each one of the plurality of priority levels include an allocated range having a floor and a ceiling of the voltage and the clock speed adjusted therebetween.

9. The system of claim 8 , wherein the at least one processor device:
statically defines, for each one of the plurality of priority levels, the range of the voltage and the clock speed allocated therein; or
automatically estimates, for each one of the plurality of priority levels, the range of the voltage and the clock speed allocated therein by analyzing a historical usage data of the respective workloads.

10. The system of claim 9 , wherein the at least one processor device analyzes the historical usage data of the respective workloads to categorize the respective workloads into one of the plurality of priority levels; and
builds workload groups comprising multiple ones of the respective workloads having a same workload priority based upon the SLA of the respective workloads; wherein the workload groups are generated on a ranked list.

11. The system of claim 8 , wherein the at least one processor device re-allocates thereby re-adjusting the voltage and the clock speed of one of the respective processor cores performing the respective workloads having a lower one of the plurality of priority levels to another one of the respective processor cores performing the respective workloads having a higher one of the plurality of priority levels.

12. The system of claim 11 , wherein the at least one processor device, upon detection of a reduction of an input capacity able to produce the initial collective power level, maintains the allocated voltage and clock speed of the respective processor cores performing the respective workloads having the higher one of the plurality of priority levels while reducing the allocated voltage and clock speed of the res

Assignees

• IBM

Inventors

• Mahindru Ruchi
• Bivens John A
• Das Koushik K
• Li Min
• Ramasamy Harigovind V
• Ruan Yaoping
• Salapura Valentina
• Schenfeld Eugen

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/4887

  involving deadlines, e.g. rate based, periodic · CPC title

• G06F1/329 Primary

  by task scheduling · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title