Semiconductor device

Patent metadata

Field	Value
Publication number	US-10833673-B2
Application number	US-201816490233-A
Country	US
Kind code	B2
Filing date	Feb 7, 2018
Priority date	Mar 10, 2017
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.

First claim

The invention claimed is:

1. An operation adjustment method for a semiconductor device comprising: a semiconductor substrate; a deep N-well formed in the semiconductor substrate; an N-well formed in the deep N-well; a P-well formed in the deep N-well; a semiconductor layer formed in a surface portion of the semiconductor substrate; and a buried dielectric layer formed between the semiconductor layer and the deep N-well to electrically isolate the semiconductor layer and the deep N-well, a pn junction being formed between the N-well and the P-well, a PMOS transistor being formed in the semiconductor layer at a position opposing to the N-well, an NMOS transistor being formed in the semiconductor layer at a position opposing to the P-well, and the method comprising steps of:
(a) obtaining a drain current-substrate bias voltage characteristic of the NMOS transistor for a source-gate voltage of 0V;
(b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic;
(c) determining an upper limit of a substrate bias voltage of the PMOS transistor as a voltage obtained by subtracting a built-in potential of the pn junction from the lowest substrate bias voltage; and
(d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit.

2. The operation adjustment method according to claim 1 , wherein the semiconductor substrate comprises a silicon substrate, and
wherein, in the (d) step, the substrate bias voltage of the PMOS transistor is determined as being higher than a voltage obtained by subtracting 1.2V from the lowest substrate bias voltage and lower than a voltage obtained by subtracting 0.7V from the lowest substrate bias voltage.

3. The operation adjustment method according to claim 1 , wherein the semiconductor substrate comprises a silicon substrate, and
wherein, in the (d) step, the substrate bias voltage of the PMOS transistor is determined as being higher than a voltage obtained by subtracting 1.0V from the lowest substrate bias voltage and lower than a voltage obtained by subtracting 0.7V from the lowest substrate bias voltage.

4. The operation adjustment method according to claim 1 , wherein the (a) step comprises:
obtaining drain current-gate voltage characteristics of the NMOS transistor for a plurality of substrate bias voltages; and
obtaining the drain current-substrate bias voltage characteristic by identifying a drain current of the NMOS transistor for a case when a source-gate voltage is 0V for each of the plurality of substrate bias voltages.

5. An operation adjustment method for a semiconductor device comprising: a semiconductor substrate; a deep P-well formed in the semiconductor substrate; an N-well formed in the deep P-well; a P-well formed in the deep P-well; a semiconductor layer formed in a surface portion of the semiconductor substrate; and a buried dielectric layer formed between the semiconductor layer and the deep P-well to electrically isolate the semiconductor layer and the deep P-well, a pn junction being formed between the N-well and the P-well, a PMOS transistor being formed in the semiconductor layer at a position opposing to the N-well, an NMOS transistor being formed in the semiconductor layer at a position opposing to the P-well, the method comprising:
(a) obtaining a drain current-substrate bias voltage characteristic of the PMOS transistor for a source-gate voltage of 0V;
(b) obtaining a highest substrate bias voltage which turns on the PMOS transistor from the drain current-substrate bias voltage characteristic;
(c) determining a lower limit of a substrate bias voltage of the NMOS transistor as a voltage obtained by adding a built-in potential of the pn junction to the highest substrate bias voltage; and
(d) determining the substrate bias voltage of the NMOS transistor as a negative voltage higher than the lower limit.

6. The operation adjustment method according to claim 5 , wherein the semiconductor substrate comprises a silicon substrate, and
wherein, in the (d) step, the substrate bias voltage of the NMOS transistor is determined as being higher than a voltage obtained by adding 0.7V to the highest substrate bias voltage and lower than a voltage obtained by adding 1.2V to the highest substrate bias voltage.

7. The operation adjustment method according to claim 5 , wherein the semiconductor substrate comprises a silicon substrate, and
wherein, in the (d) step, the substrate bias voltage of the NMOS transistor is determined as being higher than a voltage obtained by adding 0.7V to the highest substrate bias voltage and lower than a voltage obtained by adding 1.0V to the highest substrate bias voltage.

8. A semiconductor device, comprising:
a main circuit comprising a PMOS transistor and an NMOS transistor;
a substrate bias voltage generator circuit configured to generate a substrate bias voltage of the PMOS transistor; and
a control circuit configured to control the substrate bias voltage of the PMOS transistor,
wherein the main circuit comprises:
a deep N-well formed in a semiconductor substrate;
an N-well formed in the deep N-well;
a P-well formed in the deep N-well;
a semiconductor layer formed in a surface portion of the semiconductor substrate; and
a buried dielectric layer formed between the semiconductor layer and the deep N-well to electrically isolate the semiconductor layer from the deep N-well,
wherein a pn junction is formed between the N-well and the P-well,
wherein the PMOS transistor is formed in the semiconductor layer at a position opposing to the N-well,
wherein the NMOS transistor is formed in the semiconductor layer at a position opposing to the P-well,
wherein the control circuit is configured to set a substrate bias voltage of the PMOS transistor to a first voltage when the semiconductor device is placed in a first mode,
wherein the control circuit is configured to set the substrate bias voltage of the PMOS transistor to a second voltage higher than the first voltage when the semiconductor device is placed in a second mode, and
wherein the second voltage is a positive voltage lower than a voltage obtained by subtracting a built-in potential of the pn junction from a lowest substrate bias voltage which turns on the NMOS transistor when a source-gate voltage thereof is 0V.

9. The semiconductor device according to claim 8 , wherein the semiconductor substrate comprises a silicon substrate, and
wherein the second voltage is higher than a voltage obtained by subtracting 1.2V from the lowest substrate bias voltage and lower than a voltage obtained by subtracting 0.7V from the lowest substrate bias voltage.

10. The semiconductor device according to claim 8 , wherein the semiconductor substrate comprises a silicon substrate, and
wherein the second voltage is higher than a voltage obtained by subtracting 1.0V from the lowest substrate bias voltage and lower than a voltage obtained by subtracting 0.7V from the lowest substrate bias voltage.

11. A semiconductor device, comprising:
a main circuit comprising a PMOS transistor and an NMOS transistor;
a substrate bias voltage generator circuit configured to generate a substrate bias voltage of the NMOS transistor; and
a control circuit configured to control the substrate bias voltage of the NMOS transistor,
wherein the main circuit comprises:
a deep P-well formed in a semiconductor substrate;
an N-well formed in the deep P-well;
a P-well formed in the deep P-well;
a semiconductor layer formed in a surface portion of the semiconductor substrate; and
a buried dielectric layer formed between the semiconductor layer and the deep P-

Assignees

• Mitsubishi Heavy Ind Ltd
• Japan Aerospace Exploration

Inventors

• Matsuura Daisuke
• Narita Takanori
• Kato Masahiro
• Kobayashi Daisuke
• Hirose Kazuyuki
• Kawasaki Osamu
• KAKEHASHI Yuya
• Ito Taichi

Classifications

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D86/01

  Manufacture or treatment · CPC title