Semiconductor integrated circuit and adjustment method for semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-10833670-B2
Application number	US-201916527338-A
Country	US
Kind code	B2
Filing date	Jul 31, 2019
Priority date	Mar 6, 2019
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

According to one embodiment, a semiconductor integrated circuit includes a normally-on type first switching element that has a source, a drain, and a gate, a normally-off type second switching element that has a drain that is connected to the source of the first switching element, a gate that is supplied with a driving signal, and a source, a resistor that is connected between the gate of the first switching element and the source of the second switching element, a first capacitor that is connected in parallel to the resistor, and a second capacitor between the gate and the source of the first switching element.

First claim

What is claimed is:

1. A semiconductor integrated circuit, comprising:
a normally-on type first switching element that has a source, a drain, and a gate;
a normally-off type second switching element that has a drain that is connected to the source of the first switching element, a gate that is supplied with a driving signal, and a source;
a resistor with a first end connected to the gate of the first switching element and a second end connected to the source of the second switching element;
a first capacitor with a first electrode connected to the first end of the resistor and a second electrode connected to the second end of the resistor; and
a second capacitor between the gate and the source of the first switching element,
wherein a voltage at the first end of the resistor is applied to the gate of the first switching element, and the voltage is adjusted by a capacitance ratio between the first capacitor and the second capacitor.

2. The semiconductor integrated circuit according to claim 1 , wherein the first capacitor has a variable capacitor.

3. The semiconductor integrated circuit according to claim 2 , comprising a control circuit that controls a capacitance value of the first capacitor.

4. The semiconductor integrated circuit according to claim 3 , comprising an operation processing circuit that supplies the control circuit with an instruction value to change the capacitance value of the first capacitor based on a result of comparing a gate-source voltage of the first switching element at a time when the second switching element is turned on with a desired voltage value.

5. The semiconductor integrated circuit according to claim 2 , wherein the resistor has a variable resistor.

6. The semiconductor integrated circuit according to claim 2 , wherein the second capacitor is composed of a parasitic capacitor between the gate and the source of the first switching element.

7. The semiconductor integrated circuit according to claim 1 , wherein the resistor has a variable resistor.

8. The semiconductor integrated circuit according to claim 7 , comprising a control circuit that controls a resistance value of the resistor.

9. The semiconductor integrated circuit according to claim 8 , comprising an operation processing circuit that supplies the control circuit with an instruction value to change the resistance value of the resistor in such a manner that a time constant that is provided by the resistance value of the resistor and a capacitance value of the first capacitor is identical between before the capacitance value of the first capacitor is changed and after it is changed.

10. The semiconductor integrated circuit according to claim 1 , wherein the second capacitor is composed of a parasitic capacitor between the gate and the source of the first switching element.

11. The semiconductor integrated circuit according to claim 1 , wherein the second capacitor has a variable capacitor.

12. An adjustment method for a semiconductor integrated circuit including:
a normally-on type first switching element that has a source, a drain, and a gate;
a normally-off type second switching element that has a drain that is connected to the source of the first switching element, a gate that is supplied with a driving signal, and a source;
a resistor that is connected between the gate of the first switching element and the source of the second switching element;
a first capacitor that is connected in parallel to the resistor; and
a second capacitor between the gate and the source of the first switching element, comprising
a step of adjusting a capacitance value of the first capacitor depending on a gate-source voltage of the first switching element at a time when the driving signal to turn on the second switching element is applied to the gate of the second switching element.

13. The adjustment method for a semiconductor integrated circuit according to claim 12 , wherein the step of adjusting a capacitance value of the first capacitor includes a step of adjusting a capacitance value of the first capacitor in such a manner that the gate-source voltage of the first switching element at a time when the driving signal to turn on the second switching element is applied to the gate of the second switching element is a value near a threshold value of the first switching element or a value less than the threshold value.

14. The adjustment method for a semiconductor integrated circuit according to claim 12 , comprising a step of detecting a gate voltage of the first switching element and a drain voltage of the second switching element at a time when the driving signal to turn on the second switching element is applied to the gate of the second switching element.

15. The adjustment method for a semiconductor integrated circuit according to claim 12 , comprising a step of adjusting a resistance value of the resistor in response to the driving signal.

16. The adjustment method for a semiconductor integrated circuit according to claim 15 , comprising a step of adjusting a resistance value of the resistor in such a manner that a time constant that is provided by the capacitance value of the first capacitor and the resistance value of the resistor is equal to a time constant that is provided by the capacitance value of the first capacitor and the resistance value of the resistor before the capacitance value of the first capacitor is adjusted.

17. The adjustment method for a semiconductor integrated circuit according to claim 15 , comprising a step of comparing a time constant that is provided by the capacitance value of the first capacitor and the resistance value of the resistor with a preliminarily set time constant and adjusting the resistance value of the resistor depending on a result of such comparison.

18. The adjustment method for a semiconductor integrated circuit according to claim 15 , comprising:
a step of increasing the resistance value of the resistor at a time when the second switching element is switched from an off-state to an on-state; and
a step of decreasing the resistance value of the resistor at a time when the second switching element is switched from the on-state to the off-state.

19. The adjustment method for a semiconductor integrated circuit according to claim 15 , comprising a step of increasing the resistance value of the resistor after the first switching element is switched to an off-state.

20. The adjustment method for a semiconductor integrated circuit according to claim 15 , comprising a step of decreasing the resistance value of the resistor after the first switching element is switched to an on-state.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Majima Hideaki

Classifications

• H03K2217/0081

  Power supply means, e.g. to the switch driver · CPC title

• H03K2017/0803

  against radiation hardening · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H03K17/168

  in composite switches · CPC title