Power resonator with wide input voltage range for isolated power transfer

Patent metadata

Field	Value
Publication number	US-10833535-B2
Application number	US-201816141052-A
Country	US
Kind code	B2
Filing date	Sep 25, 2018
Priority date	Sep 25, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A power transfer device includes a first power supply node, a second power supply node, and an oscillator circuit configured to convert an input DC signal across the first power supply node and the second power supply node into an AC signal on a differential pair of nodes comprising a first node and a second node in response to a control signal. The oscillator circuit includes a regulated power supply node and an active shunt regulator circuit configured to clamp a peak voltage level across the regulated power supply node and the second power supply node to a clamped voltage level. The clamped voltage level is linearly related to a first voltage level on the first power supply node.

First claim

What is claimed is:

1. A power transfer device comprising:
a first power supply node;
a second power supply node; and
an oscillator circuit configured to convert an input DC signal across the first power supply node and the second power supply node into an AC signal on a differential pair of nodes comprising a first node and a second node in response to a control signal, the oscillator circuit comprising:
a regulated power supply node; and
an active shunt regulator circuit configured to clamp a peak voltage level across the regulated power supply node and the second power supply node to a clamped voltage level, the clamped voltage level being linearly related to a first voltage level on the first power supply node.

2. The power transfer device, as recited in claim 1 , wherein the active shunt regulator circuit comprises:
a diode-OR coupled to the regulated power supply node, the first node, and the second node.

3. The power transfer device, as recited in claim 2 , wherein the diode-OR comprises at least one diode-coupled laterally-diffused drain metal oxide semiconductor (LDMOS) transistor and the active shunt regulator circuit further comprises at least one regular transistor.

4. The power transfer device, as recited in claim 1 , further comprising:
wherein the active shunt regulator circuit comprises:
a first terminal coupled to the regulated power supply node;
a second terminal coupled to the second power supply node; and
a capacitor coupled to the first terminal and the second terminal, the capacitor being external to an integrated circuit die including other portions of the active shunt regulator circuit and configured to smooth a voltage signal across the regulated power supply node and second power supply node.

5. The power transfer device, as recited in claim 1 , wherein the active shunt regulator circuit is configured to limit a voltage level across the regulated power supply node and the second power supply node to k×V DD , where k is a number greater than two.

6. The power transfer device, as recited in claim 1 , wherein the active shunt regulator circuit comprises:
a first voltage divider circuit coupled to the first power supply node and the second power supply node;
a second voltage divider circuit coupled to the regulated power supply node and the second power supply node;
a gain-boosted transconductance circuit coupled to a first output of the first voltage divider circuit and a second output of the second voltage divider circuit; and
an output circuit coupled to the regulated power supply node, the first power supply node, and the second power supply node, and an output of the gain-boosted transconductance circuit, the output circuit being configured to sink current from the regulated power supply node to the second power supply node in response to a voltage on the regulated power supply node exceeding (1+k)/2 times the first voltage level, where k is a ratio of a first resistance of the first voltage divider circuit to a second resistance of the first voltage divider circuit.

7. The power transfer device, as recited in claim 6 , wherein the active shunt regulator circuit further comprises:
a degenerated differential pair of transistors coupled to the first voltage divider circuit and the second voltage divider circuit.

8. The power transfer device, as recited in claim 6 , wherein the output circuit comprises a laterally-diffused drain metal oxide semiconductor (LDMOS) transistor coupled to the regulated power supply node and the first power supply node and a regular transistor.

9. The power transfer device, as recited in claim 6 , wherein the active shunt regulator circuit further comprises:
a current source coupled to the first power supply node;
a first current mirror coupled to the current source and the second power supply node;
a second current mirror coupled to the first current mirror, the first power supply node, and the gain-boosted transconductance circuit; and
a third current mirror coupled to the second current mirror, the second power supply node, and the gain-boosted transconductance circuit.

10. The power transfer device, as recited in claim 1 , wherein the active shunt regulator circuit comprises:
a pre-charge circuit configured to pre-charge the regulated power supply node to a pre-charge voltage level, the pre-charge voltage level being V DD -V F , where V DD is an input DC voltage across the first power supply node and the second power supply node and V F is a forward voltage of a forward-biased diode coupled between the regulated power supply node and the first power supply node.

11. The power transfer device, as recited in claim 1 , wherein the oscillator circuit further comprises a first conductive coil coupled to the first node and the second node to form a primary side circuit of the power transfer device, a center tap of the first conductive coil being coupled to the first power supply node, and
wherein the oscillator circuit is configured to develop a pseudo-differential signal on the first node and the second node, the pseudo-differential signal having a peak voltage of at least three times a voltage level of an input DC voltage on the first power supply node.

12. A method comprising:
converting an input DC signal received using a first power supply node and a second power supply node into an AC signal using an oscillator circuit,
wherein the converting comprises an active shunt regulator clamping a peak voltage level across a regulated power supply node and the second power supply node to a clamped voltage level, the clamped voltage level being linearly related to a first voltage level of the input DC signal.

13. The method, as recited in claim 12 , further comprising:
pre-charging the regulated power supply node to a pre-charge voltage level, the pre-charge voltage level being less than the first voltage level; and
charging the regulated power supply node from the pre-charge voltage level to the clamped voltage level.

14. The method, as recited in claim 13 , wherein the pre-charge voltage level is V DD -V F , where V DD is the first voltage level and V F is a forward voltage of a forward-biased diode coupled between the regulated power supply node and the first power supply node.

15. The method, as recited in claim 12 , wherein the converting further comprises:
developing a pseudo-differential signal on a differential pair of nodes including a first node of the oscillator circuit and a second node of the oscillator circuit,
wherein the clamping limits a second peak voltage level of the AC signal to the clamped voltage level.

16. The method, as recited in claim 15 , further comprising:
providing to the regulated power supply node, a higher voltage signal of a first signal on the first node and a second signal on the second node.

17. The method, as recited in claim 12 , wherein the clamping comprises:
measuring the first voltage level across the first power supply node and the second power supply node to generate a first voltage measurement; and
measuring a second voltage level across the regulated power supply node and the second power supply node to generate a second voltage measurement.

18. The method, as recited in claim 17 , wherein the clamping comprises:
shunting current from the regulated power supply node to the second power supply node in response to the first voltage measurement exceeding (1+k)/2 times the second voltage measurement, where k is a ratio of a first resistance of a voltage-divider circuit used to generate the first voltage measurement to a

Assignees

• Silicon Lab Inc

Inventors

• Al-Shyoukh Mohammad
• Pentakota Krishna
• Mastovich Stefan N

Classifications

• H02J7/855

  with circuits adapted for supplying loads from the battery · CPC title

• H02M1/346

  Passive non-dissipative snubbers · CPC title

• H02M1/0058

  by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero (using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826) · CPC title

• H02J50/12 Primary

  of the resonant type · CPC title

• H02M3/33523 Primary

  with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title