Current compliance layers and memory arrays comprising thereof

Patent metadata

Field	Value
Publication number	US-10833263-B2
Application number	US-202016735801-A
Country	US
Kind code	B2
Filing date	Jan 7, 2020
Priority date	Jan 8, 2017
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.

First claim

What is claimed is:

1. A memory device, comprising:
a stack of two alternating material layers on a substrate;
a via in the stack, the via including a sidewall;
a memory cell layer disposed on the sidewall in the via; and
a current compliance layer (CCL) disposed on the memory cell layer in the via, the CCL including an interface layer and a main layer, wherein the interface layer comprises tellurium oxide and the main layer comprises germanium and tellurium.

2. The memory of claim 1 wherein the memory cell layer and the CCL are deposited with an atomic layer deposition process.

3. The memory of claim 1 wherein the main layer of the CCL includes a Copper Sulfide (CuS).

4. The memory of claim 1 wherein the main layer of the CCL includes a sulfur concentration of at least 50% atomic.

5. The memory of claim 1 , wherein a concentration of germanium in the main layer is between about 1% atomic and 10% atomic.

6. The memory of claim 1 , wherein a concentration of tellurium in the main layer is between about 80% atomic and 99% atomic.

7. The memory of claim 1 further comprising a conductive material disposed in the via.

8. A memory device, comprising:
means or depositing an interface layer of a current compliance layer (CCL) on a memory element;
means for depositing a main layer of the CCL,
wherein the interface layer directly interfaces the main layer,
wherein the interface layer comprises tellurium oxide,
wherein the main layer comprises germanium and tellurium.

Assignees

• Intermolecular Inc

Inventors

• Chiang Tony
• Barabash Sergey V
• Littau Karl
• Narasimhan Vijay Kris
• Weeks Stephen

Classifications

• G11C13/003 Primary

  Cell access · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• H01L27/249

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic