Low power 2D memory transistor for flexible electronics and the fabrication methods thereof

Patent metadata

Field	Value
Publication number	US-10833102-B2
Application number	US-201916356067-A
Country	US
Kind code	B2
Filing date	Mar 18, 2019
Priority date	Mar 18, 2019
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

Devices and methods of a transistor device that include a flexible memory cell. The flexible memory cell having a gate stack with sidewalls provided over a substrate. The gate stack including a metal gate layer provided over the substrate. A buffer layer provided over the metal gate layer. A ferroelectric layer provided over the buffer layer. A dielectric layer provided over the ferroelectric layer. Further, a two-dimensional (2D) material layer provided over a portion of a top surface of the dielectric layer. Source and drain regions provided on separate portions of the top surface of the dielectric layer so as to create a cavity that the 2D material layer are located.

First claim

What is claimed is:

1. A transistor device including a memory cell, the memory cell comprising:
a gate stack with sidewalls provided over a supporting substrate, the gate stack including:
a metal gate layer provided over the supporting substrate;
a titanium nitride (TiN) buffer layer provided between the metal gate layer and a ferroelectric layer;
and
a dielectric layer provided over the ferroelectric layer;

a two-dimensional (2D) material layer provided onto a portion of a top surface of the dielectric layer; and
source and drain regions provided on separate portions of the top surface of the dielectric layer so as to create a cavity in which the 2D material layer is positioned in the cavity.

2. The memory cell of claim 1 , wherein the 2D material layer include grown molybdenum disulfide (MoS 2 ) flakes transferred to the portion of the top surface of the dielectric layer.

3. The memory cell of claim 1 , wherein a ratio of thicknesses of the dielectric material layer and the ferroelectric layer, operatively provide tuneability of an operating voltage of the transistor device along with an ability to reduce the operating voltage of the transistor device.

4. The memory cell of claim 1 , wherein a structural configuration of the 2D material layer location positioned on a top of the gate stack, resulting a transferring of the transistor device including the supporting substrate or not including the supporting substrate, then to other substrates having material properties including one of, ductility including stretching and bending, elasticity including flexing and a tensile strength.

5. The memory cell of claim 1 , wherein the metal gate layer is a titanium (Ti)/gold (Au) layer acting as a gate electrode, the ferroelectric layer is an inorganic ferroelectric film of zirconium-doped hafnium oxide (HfZrO x ) layer, and the dielectric layer is a dielectric hafnium(IV) oxide (HfO 2 ) layer acting as a passivation layer.

6. The memory cell of claim 1 , wherein the dielectric layer is a dielectric hafnium(IV) oxide (HfO 2 ) layer that is inserted between the 2D material layer and the ferroelectric layer, such that the ferroelectric layer is inorganic ferroelectric film of zirconium-doped hafnium oxide (HfZrO x ),
such that the HfZrO x layer serves as a passivation layer as preserving a ferroelectricity of the underlying HfZrO x layer through a surface passivation, and as lowering a threshold poling voltage of the transistor device, such that a lowering of a voltage results in a change of resistance which initiates a memory effect of a state of resistance transition to either a first state of resistance or to a second state of resistance.

7. The memory cell of claim 1 , wherein the dielectric layer is a dielectric hafnium(IV) oxide (HfO 2 ) layer placed between the 2D material layer and the ferroelectric layer, and the 2D material layer is a semiconductor MoS 2 channel,
and wherein the stabilization of the ferroelectricity of the transistor device is by the addition of HfO2 layer which widens a ferroelectric hysteresis loop in polarization as a function of voltage, but also reduces fluctuations of hysteresis loop, such that the HfO 2 layer serves as a passivation layer.

8. The memory cell of claim 1 , wherein the transistor device is a single-layer MoS 2 ferroelectric field-effect transistor (FeFET), such that a structural configuration of the gate stack includes positioning the dielectric layer on the ferroelectric layer with the underlying metal gate, which the structural configuration operatively provides an amplification of a MoS 2 photoluminescence (PL).

9. The memory cell of claim 1 , wherein the transistor device is a single-layer MoS 2 ferroelectric field-effect transistor (FeFET), such that the MoS 2 FeFET driving voltage (±3V).

10. The memory cell of claim 1 , wherein the source and the drain regions provided on separate portions of the top surface of the dielectric layer, together cover at least 15% of an overall surface of the top surface of the dielectric layer.

11. The memory cell of claim 1 , wherein the 2D material layer covers at least 50% of a total overall surface of the top surface of the dielectric layer.

12. The memory cell of claim 3 , wherein the dielectric material layer is connected to the ferroelectric layer, such that a total energy of the gate stack is redistributed and an energy barrier of two polarizations in the device is reduced, and wherein a level of reduced energy barrier is controlled by a thickness ratio of dielectric material layer to the ferroelectric layer, such that the thickness ratio of the dielectric material layer to the ferroelectric layer is equal to or less than 2.

13. A transistor device having a resistive switching memory cell, the resistive switching memory cell comprising:
a gate stack with sidewalls provided over a supporting substrate, the gate stack including:
a metal gate layer provided over the supporting substrate;
a titanium nitride (TiN) buffer layer provided between the metal gate layer and a ferroelectric layer;
and
a dielectric layer provided over the ferroelectric layer;

two-dimensional (2D) materials that are a MoS 2 monolayer including grown MoS 2 flakes transferred onto a portion of a top surface of the dielectric layer; and
source and drain regions provided on separate portions of the top surface of the dielectric layer which create a cavity in which the 2D material layer is positioned in the cavity.

14. The resistive switching memory cell of claim 13 , wherein the ferroelectric layer is an inorganic ferroelectric film of zirconium-doped hafnium oxide (HfZrO x ), and the dielectric layer is a dielectric hafnium(IV) oxide (HfO 2 ) material.

15. The resistive switching memory cell of claim 13 , wherein a structural configuration of the gate stack of arranging the dielectric layer on the ferroelectric layer along with the underlying metal gate, operatively acts as a mirror layer that enhances a light-matter interaction of the MoS 2 monolayer, through an enhanced optical absorption.

16. The resistive switching memory cell of claim 13 , wherein a dynamic write/read/erase/read processes of the MoS 2 FeFET is obtained by applying alternating pulses onto the metal gate, such that voltages applied to the metal gate of dynamic write, erase, measured +3 V, −3V, and 0 V, respectively, by a measuring device, and a dynamic write/read ratio is determined as over 10 2 under various drain-to-source voltages (V DS ) equaling 0.4 V.

17. The resistive switching memory cell of claim 13 , wherein the transistor device is a single-layer MoS 2 ferroelectric field-effect transistor (FeFET), such that the MoS 2 FeFET driving voltage (±3V).

18. The resistive switching memory cell of claim 13 , wherein the source and the drain regions provided on separate portions of the top surface of the dielectric layer, together cover at least 20% of an overall surface of the top surface of the dielectric layer.

19. The resistive switching memory cell of claim 13 , wherein a structural configuration of the 2D material layer location positioned on a top of the gate stack, is arranged so the 2D material layer covers less than 70% of a total overall surface of the top surface of the dielectric layer.

20. A single-layer molybdenum disulfide (MoS 2 ) ferroelectric field-effect transistor (FeFET) including a memory cell, the memory cell comprising:
a gate stack with sidewalls provided over a supporting substrate, the gate stack including:
a metal layer acting as a metal gate prov

Assignees

• Mitsubishi Electric Res Laboratories Inc

Inventors

• Teo Koon Hoo
• Shen pin-chun
• Lin Chungwei

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title