Non-volatile in-memory computing device

Patent metadata

Field	Value
Publication number	US-10832746-B2
Application number	US-201514588419-A
Country	US
Kind code	B2
Filing date	Jan 1, 2015
Priority date	Jul 16, 2009
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array.

First claim

What is claimed is:

1. An in-memory computing device, comprising:
a memory array including non-volatile memory cells, each said non-volatile memory cell including one resistive element,
wherein each said non-volatile memory cell is connected to a word line, connecting a row of said non-volatile memory cells, and to a source line and a bit line, said bit line connecting to said resistive element and each said source line and each said bit line connecting a single column of said non-volatile memory cells;
a multiple row decoder to activate at least two word lines at a same time;
a bit line sensor, per selected bit line, to sense a parametric voltage change or a parametric current change related to resistances of said one resistive element in each activated cell of said selected bit line and to decode said parametric voltage change or said parametric current change in a qualitative manner as being a value between 1 and 0.

2. The device according to claim 1 ,
wherein said non-volatile memory cells include any one of ReRAM cells, MRAM cells, STT-RAM cells, PC-RAM cells, and PMC cells.

3. The device according to claim 1 ,
wherein said bit line sensor includes sensing circuitry to sense parametric change in any one of a change in voltage, a change in current, and a change in resistance.

4. The device according to claim 1 , further comprising:
circuitry to write data associated with said parametric voltage change or said parametric current change into said memory array,
wherein said circuitry includes a controller to instruct said multiple row decoder to activate two or more rows in said memory array.

Assignees

• Gsi Technology Inc

Inventors

• Akerib Avidan
• Ehrman Eli

Classifications

• G11C2213/82

  Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title