Method to execute successive dependent instructions from an instruction stream in a processor

Patent metadata

Field	Value
Publication number	US-10831496-B2
Application number	US-201916288644-A
Country	US
Kind code	B2
Filing date	Feb 28, 2019
Priority date	Feb 28, 2019
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

The present disclosure relates to a method to execute successive dependent instructions from an instruction stream in a processor. In an embodiment, the invention relates to a method to execute successive dependent instructions from an instruction stream in a processor. The method may include identifying a first instruction and a second instruction. A given operand of a second instruction is an output of the first instruction of the pair. The first instruction is older than the second instruction. The method may include loading the operands of the first instruction and the second instruction. The method may include executing the first instruction and the second instruction.

First claim

The invention claimed is:

1. A method to execute successive dependent instructions from an instruction stream in a processor, the method comprising:
identifying a first instruction and a second instruction, wherein a given operand of a second instruction is an output of the first instruction of the pair, and wherein the first instruction is older than the second instruction;
loading the operands of the first instruction and the second instruction;
prior to executing the first instruction and second instruction, determining whether a third instruction is dependent on the first instruction or dependent on the second instruction;
storing the result of an instruction depended on by the third instruction in a first processor cycle and the result of an instruction not depended on by the third instruction in a second processor cycle; and
executing the first instruction and the second instruction.

2. The method of claim 1 , wherein the executing of the first and second instructions is performed in respective processor cycles of two distinct instruction cycles, wherein one of the two distinct instruction cycles is the instruction cycle used for the loading.

3. The method of claim 1 , wherein the execution of the first instruction and the second instruction comprises: executing the first instruction in a first processor cycle; providing the result of the execution of the first instruction in a second processor cycle; using the result of the first instruction for executing the second instruction during the second processor cycle; and providing the result of the second instruction in a third processor cycle.

4. The method of claim 3 , further comprising invoking an instruction dependent on the result of the first instruction in the third processor cycle and invoking another instruction dependent on the result of the second instruction in a subsequent processor cycle.

5. The method of claim 1 , wherein the execution of the first instruction and the second instruction comprises: executing the second instruction in a first processor cycle; providing the result of the execution of the second instruction in a second processor cycle; executing the first instruction during the second processor cycle; and providing the result of the first instruction in a third processor cycle.

6. The method of claim 5 , being performed using a processing unit that is configured to receive as input the loaded operands.

7. The method of claim 5 , further comprising invoking an instruction dependent on the result of the second instruction in the third processor cycle and invoking another instruction dependent on the result of the first instruction in a subsequent processor cycle.

8. The method of claim 1 , further comprising storing the result of the second instruction in a first processing cycle before storing the result of the first instruction in a second processor cycle.

9. The method of claim 1 , further comprising storing the result of the first instruction in a first processor cycle before storing the result of the second instruction in a second processor cycle.

10. The method of claim 1 , further comprising:
based on determining the third instruction is dependent on the first instruction, switching into a first operation mode, wherein in the first operation mode comprises storing the result of the first instruction in a first processor cycle before storing the result of the second instruction in a second processor cycle.

11. The method of claim 1 , further comprising:
based on determining the third instruction is dependent on the second instruction switching into a second operation mode, wherein in the second operation mode comprises storing the result of the second instruction in a first processing cycle before storing the result of the first instruction in a second processor cycle.

12. The method of claim 1 , wherein the dependent instructions are different types of instructions.

13. A computer program product for execute successive dependent instructions from an instruction stream in a processor, the computer program product comprising:
one or more computer-readable storage devices and program instructions stored on at least one of the one or more tangible storage devices, the program instructions comprising:
identifying a first instruction and a second instruction, wherein a given operand of a second instruction is an output of the first instruction of the pair, and wherein the first instruction is older than the second instruction;
loading the operands of the first instruction and the second instruction;
prior to executing the first instruction and second instruction, determining whether a third instruction is dependent on the first instruction or dependent on the second instruction;
storing the result of an instruction depended on by the third instruction in a first processor cycle and the result of an instruction not depended on by the third instruction in a second processor cycle; and
executing the first instruction and the second instruction.

14. The computer program product of claim 13 , wherein the execution of the first instruction and the second instruction comprises: executing the second instruction in a first processor cycle; providing the result of the execution of the second instruction in a second processor cycle; executing the first instruction during the second processor cycle; and providing the result of the first instruction in a third processor cycle.

15. The computer program product of claim 13 , further comprising:
based on determining the third instruction is dependent on the first instruction, switching into a first operation mode, wherein in the first operation mode comprises storing the result of the first instruction in a first processor cycle before storing the result of the second instruction in a second processor cycle.

16. The computer program product of claim 13 , further comprising:
based on determining the third instruction is dependent on the second instruction switching into a second operation mode, wherein in the second operation mode comprises storing the result of the second instruction in a first processing cycle before storing the result of the first instruction in a second processor cycle.

17. A computer system for execute successive dependent instructions from an instruction stream in a processor, the computer system comprising:
one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, and program instructions stored on at least one of the one or more computer-readable devices for execution by at least one of the one or more processors via at least one of the one or more memories, the program instructions comprising:
identifying a first instruction and a second instruction, wherein a given operand of a second instruction is an output of the first instruction of the pair, and wherein the first instruction is older than the second instruction;
loading the operands of the first instruction and the second instruction;
prior to executing the first instruction and second instruction, determining whether a third instruction is dependent on the first instruction or dependent on the second instruction;
storing the result of an instruction depended on by the third instruction in a first processor cycle and the result of an instruction not depended on by the third instruction in a second processor cycle; storing the result of an instruction depended on by the third instruction in a first processor cycle and the result of an instruction not depended on by the third instruction in a second processor cycle; an

Assignees

• IBM

Inventors

• Boersma Maarten J
• Kroener Michael Klaus
• Fricke Niels
• Figuli Razvan Peter
• Szirmak Nandor
• Nguyen Dung Q

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/3824 Primary

  Operand accessing · CPC title

• G06F9/3802

  Instruction prefetching · CPC title

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title