Storage device temporarily suspending internal operation to provide short read response time for read request from host

Patent metadata

Field	Value
Publication number	US-10831405-B2
Application number	US-201815960644-A
Country	US
Kind code	B2
Filing date	Apr 24, 2018
Priority date	Sep 8, 2017
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.

First claim

What is claimed is:

1. A storage device comprising:
a first memory device connected to a first channel of a plurality of channels, the first memory device including first to fourth planes;
a second memory device connected to the first channel, the second memory device including fifth to eighth planes; and
a controller configured to communicate with one of the first memory device and the second memory device through the first channel, such that communication with the first memory device and communication with the second memory device are mutually exclusive, wherein
when the controller receives a read request for reading data stored in the fifth to eighth planes of the second memory device while the controller processes a direct memory access (DMA) write operation for transmitting data to be stored in the first to fourth planes of the first memory device to the first memory device through the first channel, the controller is further configured to suspend the DMA write operation and to transmit a read command associated with the read request to the second memory device through the first channel,
the controller is further configured to resume the suspended DMA write operation to transmit remaining data to the first memory device through the first channel, after transmitting the read command to the second memory device through the first channel, and
when a reference time lapses while the controller processes the resumed DMA write operation, the controller is further configured to re-suspend the resumed DMA write operation and processes a direct memory access (DMA) read operation for receiving the data stored in the fifth to eighth planes from the second memory device through the first channel, and
after receiving the data stored in the fifth to eighth planes from the second memory device, the controller is further configured to resume the re-suspended DMA write operation.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Chulseung
• Woo Seonghoon
• Han Kyuwook
• Kim Daehyun

Classifications

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title