Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements

Patent metadata

Field	Value
Publication number	US-10831254-B2
Application number	US-201816129417-A
Country	US
Kind code	B2
Filing date	Sep 12, 2018
Priority date	Sep 15, 2017
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.

First claim

What is claimed is:

1. A power management system for a multiple (multi-) central processing unit (CPU) processor, comprising:
a plurality of local current manager (LCM) circuits each associated with a CPU among a plurality of CPUs, each LCM circuit among the plurality of LCM circuits communicatively coupled to a global current manager (GCM) circuit;
the GCM circuit configured to:
receive a current allocation request from a LCM circuit among the plurality of LCM circuits indicating a requested current allocation for its respective CPU;
determine if the requested current allocation from the LCM circuit would cause a total current allocation for the plurality of CPUs to exceed a maximum rail current limit for a power rail configured to supply power to the plurality of CPUs; and
in response to determining that the requested current allocation from the LCM circuit would cause the total current allocation for the plurality of CPUs to exceed the maximum rail current limit for the power rail:
allocate a current allocation of the total current allocation of the power rail for each of the plurality of CPUs based on a respective performance criteria for each of the plurality of CPUs; and
communicate the determined current allocation for each of the plurality of CPUs to the plurality of LCM circuits;

each LCM circuit among the plurality of LCM circuits configured to:
receive, from the GCM circuit, the current allocation for its associated CPU set by the GCM circuit; and
determine if a workload performance of its associated CPU among the plurality of CPUs would exceed the current allocation for its associated CPU among the plurality of CPUs set by the GCM circuit; and
in response to determining the workload performance of its associated CPU among the plurality of CPUs would exceed the current allocation for its associated CPU among the plurality of CPUs set by the GCM circuit:
reduce an operating frequency of its associated CPU; and
communicate the current allocation request for additional current allocation for its associated CPU to the GCM circuit.

2. The power management system of claim 1 , wherein in response to determining that the requested current allocation from the LCM circuit would cause the total current allocation for the plurality of CPUs to exceed the maximum rail current limit for the power rail, the GCM circuit is configured to:
proportionally allocate the current allocation of the total current allocation of the power rail for each of the plurality of CPUs based on the respective performance criteria of each of the plurality of CPUs.

3. The power management system of claim 2 , wherein each LCM circuit among the plurality of LCM circuits is configured to communicate the respective performance criteria for its associated CPU among the plurality of CPUs to the CGM circuit.

4. The power management system of claim 1 , wherein the GCM circuit is further configured to set the current allocation for each CPU among the plurality of CPUs based on the respective performance criteria for each of the plurality of CPUs.

5. The power management system of claim 1 , wherein:
the GCM circuit is further configured to, in response to determining that the requested current allocation from the LCM circuit would cause the total current allocation for the plurality of CPUs to exceed the maximum rail current limit for the power rail, communicate a denial of the requested current allocation from the LCM circuit; and
each LCM circuit among the plurality of LCM circuits is further configured to, in response to receiving a denial from the GCM circuit for the additional current allocation required for its associated CPU:
receive, from the GCM circuit, a new current allocation for its associated CPU; and
adjust an operating frequency of the associated CPU based on the received new current allocation.

6. The power management system of claim 5 , wherein each LCM circuit among the plurality of LCM circuits is further configured to, in response to receiving the denial from the GCM circuit for the additional current allocation required for its associated CPU, instruct a voltage regulator circuit to adjust an operating voltage of the associated CPU based on the adjusted operating frequency.

7. The power management system of claim 1 , wherein each LCM circuit among the plurality of LCM circuits is further configured to:
monitor current consumption of its associated CPU among the plurality of CPUs;
determine if the monitored current consumption of its associated CPU among the plurality of CPUs would exceed the current allocation for its associated CPU among the plurality of CPUs set by the GCM circuit; and
in response to determining the monitored current consumption of its associated CPU among the plurality of CPUs would exceed the current allocation for its associated CPU among the plurality of CPUs set by the GCM circuit, reduce the operating frequency of its associated CPU.

8. The power management system of claim 7 , wherein each LCM circuit among the plurality of LCM circuits is further configured to, in response to determining the monitored current consumption of its associated CPU among the plurality of CPUs would exceed the current allocation for its associated CPU, communicate the current allocation request for additional current allocation for its associated CPU among the plurality of CPUs to the GCM circuit.

9. The power management system of claim 1 , wherein the GCM circuit is further configured to:
set an initial current allocation for each CPU among the plurality of CPUs; and
communicate an initial regulated voltage level to a voltage regulator circuit to set an initial regulated voltage on the power rail based on the initial current allocation for each CPU among the plurality of CPUs.

10. The power management system of claim 9 , wherein the GCM circuit is configured to set the initial current allocation for each CPU among the plurality of CPUs based on a minimum and maximum current allocation range.

11. The power management system of claim 9 , wherein the GCM circuit is configured to communicate the initial regulated voltage level to the voltage regulator circuit based on a highest operating voltage for a CPU among the plurality of CPUs, to control the initial regulated voltage on the power rail based on the initial current allocation for each CPU among the plurality of CPUs.

12. The power management system of claim 9 , wherein:
each LCM circuit among the plurality of LCM circuits is further configured to communicate an initial current allocation request for current allocation for its associated CPU among the plurality of CPUs to the GCM circuit; and
the GCM circuit is configured to set the initial current allocation for each CPU among the plurality of CPUs based on the received initial current allocation request from the plurality of CPUs.

13. The power management system of claim 12 , wherein:
each LCM circuit among the plurality of LCM circuits is further configured to communicate initial performance criteria for its associated CPU among the plurality of CPUs to the GCM circuit; and
the GCM circuit is configured to determine the initial current allocation for each CPU among the plurality of CPUs based on the initial performance criteria received from each LCM circuit among the plurality of LCM circuits.

14. The power management system of claim 1 , wherein the GCM circuit is configured to proportionally allocate the current allocation of the total current allocation of the power rail for each of the plurality of CPUs based on the respective performance criteria of each of the plurality of CPUs, based on a respective weigh

Assignees

• Qualcomm Inc

Inventors

• Priyadarshi Shivam
• Zahedi Seyedmajid
• Hower Derek Robert
• Waldspurger Carl Alan
• Bridges Jeffrey Todd
• Patel Sanjay Bhikhubhai
• Tarr Gabriel Martel
• Lin Chih Kang
• Wells Ryan Donovan
• Cain Iii Harold Wade

Classifications

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title