Systems and methods for cascading radar chips having a low leakage buffer

Patent metadata

Field	Value
Publication number	US-10830868-B2
Application number	US-201815887030-A
Country	US
Kind code	B2
Filing date	Feb 2, 2018
Priority date	Feb 25, 2015
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A cascaded radar sensor arrangement is disclosed. The arrangement includes a first buffer and a second buffer. The first buffer is within a first radar chip and includes a switch and is configured to mitigate a first leakage signal in the disabled mode. The second buffer is within a second radar chip and has a disabled mode. The second radar chip is cascaded with the first radar chip. A control unit is coupled to the first radar chip and the second radar chip and is configured to set the disabled mode for the first buffer.

First claim

What is claimed is:

1. A radar chip arrangement configured to operate in multiple modes, the arrangement comprising:
a local oscillator configured to generate a local oscillator signal when the radar chip arrangement is configured in a first mode;
a first transmit channel, the first transmit channel being configured to receive the local oscillator signal and to provide a radar transmit signal at a first transmit channel output based on the local oscillator signal when the radar chip arrangement is configured in the first mode; and
a circuit configured to disable the first transmit channel and to receive an external local oscillator signal at the first transmit channel output when the radar chip arrangement is configured in a second mode.

2. The radar chip arrangement of claim 1 , further comprising a second transmit channel and a second transmit channel output, the second transmit channel providing a second radar transmit signal based on the external local oscillator signal when the radar chip arrangement is configured in the second mode.

3. The radar chip arrangement of claim 2 , the second transmit channel being configured to provide the local oscillator signal at the second transmit channel output when the radar chip arrangement is configured in the first mode.

4. The radar chip arrangement of claim 1 , wherein the first transmit channel further includes a first power amplifier to generate the radar transmit signal when the radar chip arrangement is configured in the first mode.

5. The radar chip arrangement of claim 4 , wherein the circuit is configured to disable the first power amplifier when the radar chip arrangement is configured in the second mode.

6. The radar chip arrangement of claim 1 , wherein the first transmit channel further includes a first channel buffer coupled to the transmit channel output and the circuit is configured to enable the first buffer when the radar chip arrangement is configured in the second mode.

7. The radar chip arrangement of claim 6 , wherein the circuit is configured to disable the first channel buffer when the radar chip arrangement is configured in the first mode.

8. A method of operating a radar chip, the method comprising:
selecting a local oscillator signal from a local oscillator of the radar chip as a power distribution signal upon the radar chip being configured in a master mode;
selecting an external local oscillator signal as the power distribution signal upon the radar chip being configured in a slave mode;
generating a first radar signal using the power distribution signal by a first transmission channel upon the current mode being the master mode and outputting the signal to a transmission channel output; and
receiving the external local oscillator signal by the first transmission channel output upon the radar chip being configured in the slave mode.

9. The method of claim 8 , further comprising blocking a leakage signal from the first radar signal by a low leakage buffer.

10. The method of claim 9 , further comprising configuring a switch of the low leakage buffer to block the leakage signal.

11. The method of claim 8 , further comprising providing the local oscillator signal to a further radar chip configured in a slave mode by a second transmission channel upon the radar chip being configured in the master mode.

12. The method of claim 8 , further comprising generating a radar signal in a second transmit channel using the external local oscillator signal, upon the radar chip being configured in the slave mode.

13. The method of claim 8 , further comprising disabling a power amplifier of the first transmission channel upon the radar chip being configured in the slave mode.

14. The method of claim 8 , further comprising enabling a buffer coupled to the transmit channel output to receive the external local oscillator signal.

15. A radar chip selectively configurable to operate in multiple modes, the chip comprising:
a local oscillator configured to generate a local oscillator signal when the radar chip is selected to operate in a first mode;
a first transmit channel, the first transmit channel being configured to receive the local oscillator signal and to provide a radar transmit signal at a first transmit channel output based on the local oscillator signal when the radar chip arrangement is configured to operate in the first mode; and
a circuit configured to disable the first transmit channel and to receive an external local oscillator signal at the first transmit channel output when the radar chip is configured to operate in a second mode.

16. The radar chip of claim 15 , further comprising a second transmit channel and a second transmit channel output, the second transmit channel providing a second radar transmit signal based on the external local oscillator signal when the radar chip is configured to operate in the second mode.

17. The radar chip of claim 16 , the second transmit channel being configured to provide the local oscillator signal at the second transmit channel output when the radar chip is configured to operate in the first mode.

18. The radar chip of claim 15 , wherein the first transmit channel further includes a first power amplifier to generate the radar transmit signal when the radar chip is configured to operate in the first mode.

19. The radar chip of claim 18 , wherein the circuit is configured to disable the first power amplifier when the radar chip arrangement is configured to operate in the second mode.

20. The radar chip of claim 15 , wherein the first transmit channel further includes a first channel buffer coupled to the transmit channel output and the circuit is configured to enable the first buffer when the radar chip arrangement is configured to operate in the second mode.

21. The radar chip of claim 15 , wherein the radar chip is configured to operate in the first mode as a master and to operate in the second mode as a slave.

Assignees

• Infineon Technologies Ag

Inventors

• Li Hao
• Knapp Herbert

Classifications

• G01S13/931

  of land vehicles · CPC title

• G01S7/032 Primary

  Constructional details for solid-state radar subsystems · CPC title