Image processing apparatus

Patent metadata

Field	Value
Publication number	US-10827102-B2
Application number	US-201916529116-A
Country	US
Kind code	B2
Filing date	Aug 1, 2019
Priority date	Feb 24, 2017
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

An image processing apparatus, which includes a first physical computing circuit, configured to receive a plurality of first analog signals output by an image sensor, and perform a convolution operation on the plurality of first analog signals to obtain a second analog signal. The plurality of first analog signals are in a one-to-one correspondence with a plurality of pieces of pixel data of a to-be-recognized image. The first physical computing circuit comprises at least one multiplication circuit array and at least one subtraction circuit, the at least one multiplication circuit array is in a one-to-one correspondence with the at least one subtraction circuit, a multiplication circuit in each multiplication circuit array comprises a differential pair transistor, each multiplication circuit array implements the convolution operation on the plurality of first analog signals using a plurality of multiplication circuits and a corresponding subtraction circuit.

First claim

What is claimed is:

1. An image processing apparatus, comprising:
a first physical computing circuit comprising:
a receiver configured to receive a plurality of first analog signals output by an image sensor, wherein the plurality of first analog signals are in a one-to-one correspondence with a plurality of pieces of pixel data of a to-be-recognized image; and
at least one multiplication circuit array comprising:
a plurality of subtraction circuits; and
a plurality of multiplication circuits in a one-to-one correspondence with at least one subtraction circuit, wherein each multiplication circuit comprises a differential pair transistor and is configured to perform a convolution operation on the plurality of first analog signals to obtain a second analog signal using a convolution kernel, wherein the convolution kernel is based on a differential input voltage of a plurality of differential pair transistors comprised in each of the at least one multiplication circuit array, wherein each of the at least one multiplication circuit array has a different convolution kernel, and wherein the second analog signal indicates a recognition result of the to-be-recognized image.

2. The image processing apparatus according to claim 1 , wherein each differential pair transistor comprises a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor, and wherein the first MOS transistor and the second MOS transistor work in a subthreshold region.

3. The image processing apparatus according to claim 2 , wherein the at least one subtraction circuit comprises two input interfaces, one output interface, two P-channel current mirrors (PMIRs), and one N-channel current mirror (NMIR), wherein a drain of the first MOS transistor comprised in each differential pair transistor is a first output interface of a corresponding multiplication circuit, wherein a drain of the second MOS transistor comprised in each differential pair transistor is a second output interface of the corresponding multiplication circuit, wherein first output interfaces of all the multiplication circuits in the at least one multiplication circuit array are connected to one input interface of the at least one subtraction circuit, and second output interfaces of all the multiplication circuits in the multiplication circuit array are connected to another input interface of the at least one subtraction circuit, wherein one input interface of the at least one subtraction circuit is connected to the output interface of the at least one subtraction circuit through one of the two PMIRs, and wherein the other input interface of the at least one subtraction circuit is connected to the output interface of the at least one subtraction circuit through another one of the two PMIRs and the NMIR.

4. The image processing apparatus according to claim 1 , further comprising a second physical computing circuit configured to perform a pooling operation on the second analog signal to obtain a third analog signal, wherein the second physical computing circuit comprises a current mirror circuit.

5. The image processing apparatus according to claim 4 , wherein there are a plurality of second analog signals, wherein the second physical computing circuit comprises at least one current mirror circuit, wherein the at least one current mirror circuit is in a one-to-one correspondence with the at least one multiplication circuit array, and wherein each current mirror circuit is configured to perform the pooling operation on the second analog signal that is output by a corresponding multiplication circuit array.

6. The image processing apparatus according to claim 4 , further comprising a fifth physical computing circuit, wherein an input interface of the fifth physical computing circuit is connected to an output interface of the second physical computing circuit to perform non-linear mapping processing on the third analog signal.

7. The image processing apparatus according to claim 6 , wherein the fifth physical computing circuit comprises a fifth MOS transistor and a sixth MOS transistor, and wherein the fifth MOS transistor and the sixth MOS transistor work in a subthreshold region.

8. The image processing apparatus according to claim 4 , wherein the pooling operation is an average pooling operation.

9. The image processing apparatus according to claim 1 , further comprising:
a third physical computing circuit, wherein an input interface of the third physical computing circuit is connected to an output interface of the first physical computing circuit to perform non-linear mapping processing on the second analog signal to obtain a fourth analog signal; and
a fourth physical computing circuit, wherein an input interface of the fourth physical computing circuit is connected to an output interface of the third physical computing circuit to perform a pooling operation on the fourth analog signal, and wherein the fourth physical computing circuit comprises a current mirror circuit.

10. The image processing apparatus according to claim 9 , wherein the third physical computing circuit comprises a circuit comprising a third metal-oxide-semiconductor (MOS) transistor and a fourth MOS transistor, and wherein the third MOS transistor and the fourth MOS transistor work in a subthreshold region.

11. A first physical computer, comprising:
a receiver configured to receive a plurality of first analog signals output by an image sensor, wherein the plurality of first analog signals are in a one-to-one correspondence with a plurality of pieces of pixel data of a to-be-recognized image; and
at least one multiplication circuit array comprising:
at least one subtraction circuit; and
a plurality of multiplication circuits in a one-to-one correspondence with the at least one subtraction circuit, wherein each multiplication circuit comprises a differential pair transistor and is configured to perform a convolution operation on the plurality of first analog signals to obtain a second analog signal using a convolution kernel, wherein the convolution kernel is based on a differential input voltage of a plurality of differential pair transistors comprised in each of the at least one multiplication circuit array, wherein each of the at least one multiplication circuit array has a different convolution kernel, and wherein the second analog signal indicates a recognition result of the to-be-recognized image.

12. The first physical computer according to claim 11 , wherein each differential pair transistor comprises a first metal-oxide semiconductor (MOS) transistor and a second MOS transistor, and wherein the first MOS transistor and the second MOS transistor work in a subthreshold region.

13. The first physical computer according to claim 12 , wherein the at least one subtraction circuit comprises two input interfaces, one output interface, two P-channel current mirrors (PMIRs), and one N-channel current mirror (NMIR), wherein a drain of the first MOS transistor comprised in each differential pair transistor is used as a first output interface of a corresponding multiplication circuit, wherein a drain of the second MOS transistor comprised in each differential pair transistor is used as a second output interface of the corresponding multiplication circuit, wherein first output interfaces of all the multiplication circuits in the at least one multiplication circuit array are connected to one input interface of the at least one subtraction circuit, and second output interfaces of all the multiplication circuits in the multiplication circuit array are connected to another input interface of the at least one subtraction circuit, wherein one input interface of the

Assignees

• Huawei Tech Co Ltd

Inventors

• Qiao Fei
• Jia Kaige
• Liu Zheyu
• Wei Qi
• Chen Hai

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G05F3/262 Primary

  using field-effect transistors only · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• G06N3/08

  Learning methods · CPC title

• H04N5/14 Primary

  Picture signal circuitry for video frequency region (cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00) · CPC title