Integrator circuit for use in a sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-10826522-B2
Application number	US-201816615505-A
Country	US
Kind code	B2
Filing date	May 16, 2018
Priority date	May 24, 2017
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

An integrator circuit ( 10 ) for use in a sigma-delta modulator ( 1 ) comprises a differential operational amplifier ( 130 ) with a first input node (E 130 a ) and a second input node (E 130 b ). The first input node (E 130 a ) of the differential operational amplifier ( 130 ) is connected to a first current path ( 101 ) and the second input node (E 130 b ) of the differential operational amplifier ( 130 ) is connected to a second current path ( 102 ). A first controllable switch ( 111 ) is arranged between the second input node (E 130 b ) of the differential operational amplifier ( 130 ) and the first current path ( 101 ). A second controllable switch ( 112 ) is arranged between the first input node (E 130 a ) of the differential operational amplifier ( 130 ) and the second current path ( 102 ). A third controllable switch ( 113 ) is arranged between a reference potential (RP) and the first current path ( 101 ). A fourth controllable switch ( 114 ) is arranged between the reference potential (RP) and the second current path ( 102 ).

First claim

The invention claimed is:

1. An integrator circuit for use in a sigma-delta modulator, the integrator circuit comprising:
a first current path having a first signal input terminal configured to apply a first input signal,
a second current path having a second signal input terminal configured to apply a second input signal,
a differential operational amplifier with a first input node and a second input node,
a switching network comprising:
a first set of controllable switches configured to selectively connect one of the first or the second input terminal to one of the first or the second input node of the differential operational amplifier, and
a second set of controllable switches configured to couple the first and the second current path to a reference potential,

a switching controller configured to control one of a conductive switching state or a non-conductive switching state of the first and the second sets of the controllable switches by generating switching signals during a first operational phase and a subsequent second operational phase of the integrator circuit,
wherein the first input node of the differential operational amplifier is connected to the first current path and the second input node of the differential operational amplifier is connected to the second current path,
wherein the first set of controllable switches comprises:
a first controllable switch arranged between the second input node of the differential operational amplifier and the first current path, and
a second controllable switch arranged between the first input node of the differential operational amplifier and the second current path,

wherein the second set of controllable switches comprises:
a third controllable switch arranged between a reference potential and the first current path, and
a fourth controllable switch arranged between the reference potential and the second current path,

wherein the switching controller is configured to generate a first switching signal, a delayed first switching signal, a second switching signal, and a delayed second switching signal for controlling the first set of controllable switches, wherein the delayed first switching signal is delayed in relation to the first switching signal, wherein the delayed second switching signal is delayed in relation to the second switching signal, and
wherein the switching controller is configured to generate a third switching signal for controlling the second set of controllable switches independently from the generation of the first and the second switching signals and the first and the second delayed switching signals.

2. The integrator circuit of claim 1 , comprising:
a first output terminal and a second output terminal configured to generate an output signal between the first and the second output terminals, and
a first integrating capacitor and a second integrating capacitor,
wherein the differential operational amplifier has a first output node connected to the first output terminal and a second output being connected to the second output terminal,
wherein the first integrating capacitor is arranged between the first input node and the first output node of the differential operational amplifier, and
wherein the second integrating capacitor is arranged between the second input node and the second output node of the differential operational amplifier.

3. The integrator circuit of claim 2 , comprising:
a first sampling capacitor and a second sampling capacitor,
wherein the first sampling capacitor is arranged in the first current path between the first signal input terminal and the first integrating capacitor, and
wherein the second sampling capacitor is arranged in the second current path between the second signal input terminal and the second integrating capacitor.

4. The integrator circuit of claim 3 , comprising:
a fifth controllable switch and a sixth controllable switch,
wherein the fifth controllable switch is arranged in the first current path between the first integrating capacitor and the first sampling capacitor,
wherein the sixth controllable switch is arranged in the second current path between the second integrating capacitor and the second sampling capacitor.

5. The integrator circuit of claim 4 , comprising:
a seventh controllable switch and an eighth controllable switch,
wherein the seventh controllable switch is arranged between the first signal input terminal and the first sampling capacitor,
wherein the eighth controllable switch is arranged between the second signal input terminal and the second sampling capacitor.

6. The integrator circuit of claim 5 , comprising:
a ninth controllable switch and a tenth controllable switch,
wherein the ninth controllable switch is arranged between the second signal input terminal and a position of the first current path, said position of the first current path being located between the seventh controllable switch and the first sampling capacitor,
wherein the tenth controllable switch is arranged between the first signal input terminal and a position of the second current path, said position of the second current path being located between the eighth controllable switch and the second sampling capacitor.

7. The integrator circuit of claim 6 ,
wherein the switching controller is configured to generate the first switching signal with a first level during the first operational phase and the delayed first switching signal with the first level during the first operational phase, and
wherein the switching controller is configured to generate the first switching signal and the first delayed switching signal with a respective second level during the second operational phase.

8. The integrator circuit of claim 7 ,
wherein the fifth and the sixth controllable switches are configured to be controlled by the first switching signal,
wherein the fifth and the sixth controllable switches are configured to be operated in the conductive switching state when the first switching signal is generated by the switching controller with the first level and to be operated in the non-conductive switching state, when the first switching signal is generated by the switching controller with the second level.

9. The integrator circuit of claim 7 ,
wherein the ninth and the tenth controllable switches are configured to be controlled by the first delayed switching signal,
wherein the ninth and the tenth controllable switches are configured to be operated in the conductive switching state when the delayed first switching signal is generated by the switching controller with the first level and to be operated in the non-conductive switching state when the delayed first switching signal is generated by the switching controller with the second level.

10. The integrator circuit of claim 5 ,
wherein the switching controller is configured to generate the second switching signal with a first level during the second operational phase and the delayed second switching signal with the first level during the second operational phase,
wherein the switching controller is configured to generate the second switching signal and the second delayed switching signal with a respective second level during the first operational phase.

11. The integrator circuit of claim 10 ,
wherein the first and the second controllable switches are configured to be controlled by the second switching signal,
wherein the first and the second controllable switches are configured to be operated in the conductive switching state when the second switching signal is generated by the switching controller with the first level and to be operated in the non-conductive switching state when the second switching

Assignees

• Ams Ag

Inventors

• Horii Daisuke

Classifications

• H03M3/368

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title

• H03M3/342 Primary

  by double sampling, e.g. correlated double sampling · CPC title

• H03M3/406 Primary

  by the use of a pair of integrators forming a closed loop · CPC title