Combined resistance circuit and variable gain amplifier circuit

Patent metadata

Field	Value
Publication number	US-10826451-B2
Application number	US-201816152505-A
Country	US
Kind code	B2
Filing date	Oct 5, 2018
Priority date	Oct 6, 2017
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A combined resistance circuit 2 A includes a first circuitry 20 A provided between a first end 2 a and a second end 2 b . This first circuitry 20 A includes a resistor R 1 provided between a node N 11 and a node N 12 , a resistor R 2 provided between the node N 12 and a node N 13 , a resistor R 3 provided between the node N 13 and a node N 14 , a resistor R 4 provided between the node N 14 and the node N 11 , a resistor R 5 provided between the node N 11 and the node N 13 , a switch SW 0 provided in series to the resistor R 4 between the node N 14 and the node N 11 , and a switch SW 1 provided in series to the resistor R 2 between the node N 12 and the node N 13 . The node N 12 is connected to the first end and the node N 14 is connected to the second end.

First claim

What is claimed is:

1. A combined resistance circuit comprising:
a first circuitry provided between a first end and a second end,
wherein the first circuitry includes
a first resistor (R 1 ) provided between a first node (N 11 ) and a second node (N 12 ),
a second resistor (R 2 ) provided between the second node (N 12 ) and a third node (N 13 ),
a third resistor (R 3 ) provided between the third node (N 13 ) and a fourth node (N 14 ),
a fourth resistor (R 4 ) provided between the fourth node (N 14 ) and the first node (N 11 ),
a fifth resistor (R 5 ) provided between the first node (N 11 ) and the third node (N 13 ),
a first switch (SW 0 ) provided in series to the fourth resistor (R 4 ) between the fourth node (N 14 ) and the first node (N 11 ), and
a second switch (SW 1 ) provided in series to the second resistor (R 2 ) between the second node (N 12 ) and the third node (N 13 ),
the second node (N 12 ) is connected to the first end, and the fourth node (N 14 ) is connected to the second end.

2. The combined resistance circuit according to claim 1 ,
wherein a resistance ratio r 3 /r 1 and a resistance ratio r 4 /r 2 are equal to each other, where,
r 1 indicates a resistance value of the first resistor (R 1 ),
r 2 indicates a resistance value of the second resistor (R 2 ),
r 3 indicates a resistance value of the third resistor (R 3 ), and
r 4 indicates a resistance value of the fourth resistor (R 4 ).

3. The combined resistance circuit according to claim 1 , further comprising:
a second circuitry provided in parallel to the first circuitry between the first end and the second end,
wherein the second circuitry includes
a sixth resistor (R 6 ) provided between a fifth node (N 21 ) and a sixth node (N 22 ),
a seventh resistor (R 7 ) provided between the sixth node (N 22 ) and a seventh node (N 23 ),
an eighth resistor (R 8 ) provided between the seventh node (N 23 ) and an eighth node (N 24 ),
a ninth resistor (R 9 ) provided between the eighth node (N 24 ) and the fifth node (N 21 ),
a tenth resistor (R 10 ) provided between the fifth node (N 21 ) and the seventh node (N 23 ),
a third switch (SW 2 ) provided in series to the sixth resistor (R 6 ) between the fifth node (N 21 ) and the sixth node (N 22 ),
a fourth switch (SW 3 ) provided in series to the ninth resistor (R 9 ) between the eighth node (N 24 ) and the fifth node (N 21 ), and
a fifth switch (SW 4 ) provided in series to the seventh resistor (R 7 ) between the sixth node (N 22 ) and the seventh node (N 23 ),
the sixth node (N 22 ) is connected to the first end, and
the eighth node (N 24 ) is connected to the second end.

4. The combined resistance circuit according to claim 1 , further comprising:
a third circuitry provided in parallel to the first circuitry between the first end and the second end,
wherein the third circuitry includes
a sixth resistor (R 6 ) provided between a fifth node (N 21 ) and a sixth node (N 22 ),
a seventh resistor (R 7 ) provided between the sixth node (N 22 ) and a seventh node (N 23 ),
an eighth resistor (R 8 ) provided between the seventh node (N 23 ) and an eighth node (N 24 ),
a ninth resistor (R 9 ) provided between the eighth node (N 24 ) and the fifth node (N 21 ),
a tenth resistor (R 10 ) provided between the fifth node (N 21 ) and the seventh node (N 23 ),
a third switch (SW 2 ) provided in series to the tenth resistor (R 10 ) between the fifth node (N 21 ) and the seventh node (N 23 ),
a fourth switch (SW 3 ) provided in series to the ninth resistor (R 9 ) between the eighth node (N 24 ) and the fifth node (N 21 ), and
a fifth switch (SW 4 ) provided in series to the seventh resistor (R 7 ) between the sixth node (N 22 ) and the seventh node (N 23 ),
the sixth node (N 22 ) is connected to the first end, and
the eighth node (N 24 ) is connected to the second end.

5. The combined resistance circuit according to claim 1 , further comprising: a fourth circuitry provided in parallel to the first circuitry between the first end and the second end,
wherein the fourth circuitry includes
a sixth resistor (R 6 ) provided between a fifth node (N 21 ) and a sixth node (N 22 ),
a seventh resistor (R 7 ) provided between the sixth node (N 22 ) and a seventh node (N 23 ),
an eighth resistor (R 8 ) provided between the seventh node (N 23 ) and an eighth node (N 24 ),
a ninth resistor (R 9 ) provided between the eighth node (N 24 ) and the fifth node (N 21 ),
a tenth resistor (R 10 ) provided between the fifth node (N 21 ) and the seventh node (N 23 ),
a third switch (SW 2 ) provided between the eighth node (N 24 ) and the second end,
a fourth switch (SW 3 ) provided in series to the ninth resistor (R 9 ) between the eighth node (N 24 ) and the fifth node (N 21 ), and
a fifth switch (SW 4 ) provided in series to the seventh resistor (R 7 ) between the sixth node (N 22 ) and the seventh node (N 23 ), and
the sixth node (N 22 ) is connected to the first end.

6. A variable gain amplifier circuit, comprising:
the combined resistance circuit according to claim 1 ,
wherein the variable gain amplifier circuit outputs an electrical signal having a value corresponding to a value of an input electrical signal and a combined resistance value of the combined resistance circuit.

Assignees

• Thine Electronics Inc

Inventors

• Gendai Yuji

Classifications

• H03G3/001

  Digital control of analog signals · CPC title

• H03G1/0029

  using field-effect transistors [FET] · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45528

  the FBC comprising one or more passive resistors and being coupled between the LC and the IC · CPC title

• H03G1/0088 Primary

  using discontinuously variable devices, e.g. switch-operated · CPC title