Thin-film transistor panel

US10825840B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10825840-B2
Application numberUS-201615061291-A
CountryUS
Kind codeB2
Filing dateMar 4, 2016
Priority dateFeb 18, 2009
Publication dateNov 3, 2020
Grant dateNov 3, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of the present disclosure provide a thin-film transistor (TFT) panel structured to prevent the deterioration of image quality due to the luminance change of backlight. According to an embodiment, the TFT panel includes: an insulating substrate; a first gate line and a first data line which are formed on the insulating substrate to be insulated from each other and cross each other; a first subpixel electrode which is formed on the insulating substrate and connected to the first gate line and the first data line by a first TFT; a second subpixel electrode which is formed on the insulating substrate and separated from the first subpixel electrode; a connecting electrode which is directly connected to any one of the first and second subpixel electrodes and capacitively coupled to the other one of the first and second subpixel electrodes; a semiconductor pattern which is formed between the connecting electrode and the insulating substrate; and a light-shielding pattern which is formed between the semiconductor pattern and the insulating substrate, is overlapped by the connecting electrode, and blocks light.

First claim

Opening claim text (preview).

What is claimed is: 1. A thin-film transistor (TFT) panel comprising: an insulating substrate; a first TFT including: a first gate line including a gate electrode formed on an upper surface of the insulating substrate, a gate insulating layer formed on the gate electrode, the gate insulating layer including a lower surface facing the insulating substrate and an upper surface opposite to the lower surface, a semiconductor layer formed on the upper surface of the gate insulating layer, a first data line having a source electrode that overlaps the semiconductor layer, and a drain electrode comprising a first end, and a second end wherein the first end of the drain electrode overlaps the semiconductor layer, a first subpixel electrode formed on the insulating substrate, wherein the second end of the drain electrode is connected to the first subpixel electrode via a contact hole; a light-shielding pattern that is separate and distinct from the gate electrode and the first gate line; a second TFT: and a second subpixel electrode electrically connected to the second TFT, wherein a channel is formed between the source electrode and the drain electrode; wherein the drain electrode is disposed between the light-shielding pattern and the pixel electrode, wherein an area of the drain electrode, that is disposed between and separate from the first end and the second end of the drain electrode, overlaps the light-shielding pattern and is overlapped by the second subpixel electrode, wherein the semiconductor layer is disposed between the light-shielding pattern and the drain electrode, wherein the light-shielding pattern and the first gate line are disposed directly on the upper surface of the insulating substrate, wherein the light-shielding pattern and the first gate line directly contact the lower surface of the gate insulating layer, wherein the semiconductor layer directly contacts the upper surface of the gate insulating layer, and wherein the gate electrode, the first gate line, and the light-shielding pattern are made of a same material. 2. The panel of claim 1 , wherein the light-shielding pattern and the first gate line are both disposed between the insulating substrate and the gate insulating layer.

Assignees

Inventors

Classifications

  • having light shields · CPC title

  • using masks, e.g. half-tone masks · CPC title

  • characterised by multiple TFTs · CPC title

  • characterised by their geometrical arrangement · CPC title

  • Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title

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Frequently asked questions

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What does patent US10825840B2 cover?
Embodiments of the present disclosure provide a thin-film transistor (TFT) panel structured to prevent the deterioration of image quality due to the luminance change of backlight. According to an embodiment, the TFT panel includes: an insulating substrate; a first gate line and a first data line which are formed on the insulating substrate to be insulated from each other and cross each other; a…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/13624. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 03 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).