Interface system and display device including the same

Patent metadata

Field	Value
Publication number	US-10825416-B2
Application number	US-201916401088-A
Country	US
Kind code	B2
Filing date	May 1, 2019
Priority date	Jun 21, 2018
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

An interface system may include a transmitter and a receiver, which are coupled to each other through transmission lines, wherein the transmitter includes a transmission controller configured to transmit a reset signal to the receiver, wherein the receiver includes a reset unit configured to reset input common mode voltages of the transmission lines, based on the reset signal, and wherein the transmission lines include a first transmission line for transmitting a signal having a first phase, and a second transmission line for transmitting a signal having a second phase that is different from the first phase.

First claim

What is claimed is:

1. An interface system comprising a transmitter and a receiver, which are coupled to each other through transmission lines,
wherein the transmitter comprises a transmission controller configured to transmit a reset signal to the receiver,
wherein the receiver comprises a reset unit configured to reset input common mode voltages of the transmission lines, based on the reset signal, and
wherein the transmission lines comprise a first transmission line for transmitting a signal having a first phase, and a second transmission line for transmitting a signal having a second phase that is different from the first phase.

2. The interface system of claim 1 , wherein the reset unit comprises a first reference switch and a second reference switch, which are configured to be turned on when the reset signal is supplied,
wherein the first reference switch is coupled between a reference power source and the first transmission line, and
wherein the second reference switch is coupled between the reference power source and the second transmission line.

3. The interface system of claim 2 , wherein the reference power source has a ground voltage.

4. The interface system of claim 2 , wherein the reset unit comprises a bias voltage supply unit coupled between a driving power source and a first driving switch, and coupled between the driving power source and a second driving switch, the first and second driving switches being configured to be turned on when the reset signal is not supplied,
wherein the first driving switch is coupled between the bias voltage supply unit and the first transmission line, and
wherein the second driving switch is coupled between the bias voltage supply unit and the second transmission line.

5. The interface system of claim 1 , wherein each of the first transmission line and the second transmission line comprise a coupling capacitor.

6. The interface system of claim 1 , wherein the first phase and the second phase are opposite to each other.

7. The interface system of claim 1 , wherein the transmission controller is configured to periodically transmit the reset signal to the receiver according to a reset period.

8. The interface system of claim 7 , wherein the transmitter further comprises a signal transmitter configured to transmit a data signal having a worst pattern to the receiver when the transmitter is powered on, and
wherein the transmission controller is configured to transmit a lock start signal to the receiver while the data signal is being transmitted,
wherein the worst pattern is any one of a white pattern and a black pattern.

9. The interface system of claim 8 , wherein the receiver further comprises a clock data recovery (CDR) circuit configured to transmit a lock fail signal to the transmitter when a balance fail occurs corresponding to the data signal.

10. The interface system of claim 9 , wherein the transmitter further comprises a balance fail detector configured to generate a balance fail signal based on the lock start signal and the lock fail signal.

11. The interface system of claim 10 , wherein the transmission controller is configured to measure a balance fail time representing a time for which the balance fail signal is supplied.

12. The interface system of claim 11 , wherein the transmission controller is configured to set, to the reset period, a value obtained by dividing K (K is a natural number larger than 1) into the balance fail time.

13. A display device comprising:
a display unit comprising pixels arranged at crossing regions of scan lines and data lines;
a data driver configured to supply data signals to the data lines; and
a timing controller configured to communicate with the data driver through an interface system,
wherein the interface system comprises a transmitter and a receiver, which are coupled to each other through transmission lines,
wherein the transmitter comprises a transmission controller configured to transmit a reset signal to the receiver,
wherein the receiver comprises a reset unit configured to reset input common mode voltages of the transmission lines based on the reset signal, and
wherein the transmission lines comprise a first transmission line for transmitting a signal having a first phase, and a second transmission line for transmitting a signal having a second phase that is different from the first phase.

14. The display device of claim 13 , wherein the reset unit comprises a first reference switch and a second reference switch, which are configured to be turned on when the reset signal is supplied,
wherein the first reference switch is coupled between a reference power source and the first transmission line, and
wherein the second reference switch is coupled between the reference power source and the second transmission line.

15. The display device of claim 14 , wherein the reset unit further comprises a bias voltage supply unit coupled between a driving power source and a first driving switch, and coupled between the driving power source and a second driving switch, the first and second driving switches being configured to be turned on when the reset signal is not supplied,
wherein the first driving switch is coupled between the bias voltage supply unit and the first transmission line, and
wherein the second driving switch is coupled between the bias voltage supply unit and the second transmission line.

16. The display device of claim 15 , wherein the transmission controller is configured to periodically transmit the reset signal to the receiver according to a reset period.

17. The display device of claim 16 , wherein the transmitter further comprises a signal transmitter configured to transmit a data signal having a worst pattern to the receiver when the transmitter is powered on, and
wherein the transmission controller is configured to transmit a lock start signal to the receiver while the data signal is being transmitted
wherein the worst pattern is any one of a white pattern and a black pattern.

18. The display device of claim 17 , wherein the receiver further comprises a CDR circuit configured to transmit a lock fail signal to the transmitter when a balance fail occurs corresponding to the data signal.

19. The display device of claim 18 , wherein the transmitter further comprises a balance fail detector configured to generate a balance fail signal based on the lock start signal and the lock fail signal, and
wherein the transmission controller is configured to measure a balance fail time representing a time for which the balance fail signal is supplied, and is configured to set the reset period based on the balance fail time.

Assignees

• Samsung Display Co Ltd

Inventors

• Pyun Ki Hyun
• Yun Jong Young

Classifications

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G09G3/2096 Primary

  Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title