Shift register unit, shift register circuit, driving method therefor, and display panel

Patent metadata

Field	Value
Publication number	US-10825397-B2
Application number	US-201816098831-A
Country	US
Kind code	B2
Filing date	Mar 21, 2018
Priority date	Mar 22, 2017
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

The present disclosure relates to a shift register unit. The shift register unit includes a first input circuit configured to transmit a first voltage signal to a pull-up node, a pull-up circuit configured to transmit a first clock signal to a signal output terminal, a first pull-down control circuit configured to transmit a second clock signal to a pull-down node, a second pull-down control circuit configured to transmit a second voltage signal to the pull-down node, a pull-up control circuit configured to transmit the second voltage signal to the pull-up node, a pull-down circuit configured to transmit the second voltage signal to the signal output terminal, and a holding circuit configured to maintain the pull-up node at a low level and/or maintain the pull-down node at a high level under control of a second input.

First claim

What is claimed is:

1. A shift register unit, comprising:
a first input circuit configured to transmit a first voltage signal to a pull-up node under control of a first input signal;
a pull-up circuit configured to transmit a first clock signal to a signal output terminal under control of a voltage signal of the pull-up node;
a first pull-down control circuit configured to transmit a second clock signal to a pull-down node under control of the second clock signal;
a second pull-down control circuit configured to transmit a second voltage signal to the pull-down node under control of the voltage signal of the pull-up node;
a pull-up control circuit configured to transmit the second voltage signal to the pull-up node under control of a voltage signal of the pull-down node;
a pull-down circuit configured to transmit the second voltage signal to the signal output terminal under control of the voltage signal of the pull-down node; and
a holding circuit comprising at least one of a first holding unit and a second holding unit;
wherein the first holding unit is configured to transmit the second voltage signal to the pull-up node under control of the second input signal during a V-blank time period, the V-blank time period is a time period after a last stage of shift register unit outputs a high level signal in each frame;
wherein the second holding unit is configured to transmit the second input signal to the pull-down node under control of the second input signal during the V-blank time period;
wherein the shift register unit further comprises a third pull-down control circuit configured to transmit the second voltage signal to the pull-down node under control of a voltage signal of the signal output terminal.

2. The shift register unit of claim 1 , further comprising:
a second input circuit configured to transmit a third voltage signal to the pull-up node under control of a third input signal.

3. The shift register unit of claim 2 , wherein the second input circuit comprises:
an eighth switching element, wherein a control terminal of the eighth switching element receives the third input signal, a first terminal of the eighth switching element receives the third voltage signal, and a second terminal of the eighth switching element is connected to the pull-up node.

4. The shift register unit of claim 1 , wherein the first input circuit comprises:
a first switching element, wherein a control terminal of the first switching element receives the first input signal, a first terminal of the first switching element receives the first voltage signal, and a second terminal of the first switching element is connected to the pull-up node.

5. The shift register unit of claim 1 , wherein the pull up circuit comprises:
a second switching element, wherein a control terminal of second switching element is connected to the pull-up node, a first terminal of the second switching element receives the first clock signal, and a second terminal of the second switching element is connected to the signal output terminal; and
a first capacitor, wherein a first terminal of the first capacitor is connected to the pull-up node, and a second terminal of the first capacitor is connected to the signal output terminal.

6. The shift register unit of claim 1 , wherein:
the first pull-down control circuit comprises:
a third switching element, wherein a control terminal of the third switching element receives the second clock signal, a first terminal of the third switching element receives the second clock signal, and a second terminal of the third switching element is connected to the pull-down node;
the second pull-down control circuit comprises:
a fourth switching element, wherein a control terminal of the fourth switching element is connected to the pull-up node, a first terminal of the fourth switching element receives the second voltage signal, and a second terminal of the fourth switching element is connected to the pull-down node;
the third pull-down control circuit comprises:
a fifth switching element, wherein a control terminal of the fifth switching element is connected to the signal output terminal, a first terminal of the fifth switching element receives the second voltage signal, and a second terminal of the fifth switching element is connected to the pull-down node.

7. The shift register unit of claim 1 , wherein the pull-up control circuit comprises:
a sixth switching element, wherein a control terminal of the sixth switching element is connected to the pull-down node, a first terminal of the sixth switching element receives the second voltage signal, and a second terminal of the sixth switching element is connected to the pull-up node.

8. The shift register unit of claim 1 , wherein the pull-down circuit comprises:
a seventh switching element, wherein a control terminal of the seventh switching element is connected to the pull-down node, a first terminal of the seventh switching element receives the second voltage signal, and a second terminal of the seventh switching element is connected to the signal output terminal; and
a second capacitor, wherein a first terminal of the second capacitor is connected to the pull-down node, and a second terminal of second capacitor receives the second voltage signal.

9. The shift register unit of claim 1 , wherein:
the first holding unit comprises:
a ninth switching element, wherein a control terminal of the ninth switching element receives the second input signal, a first terminal of the ninth switching element receives the second voltage signal, and a second terminal of the ninth switching element is connected to the pull-up node;
the second holding unit includes:
a tenth switching element, where a control terminal of the tenth switching element receives the second input signal, a first terminal of the tenth switching element receives the second input signal, and a second terminal of the tenth switching element is connected to the pull-down node.

10. A shift register circuit, comprising a plurality of cascaded shift register units;
wherein each of the shift register units comprises:
a first input circuit configured to transmit a first voltage signal to a pull-up node under control of a first input signal;
a pull-up circuit configured to transmit a first clock signal to a signal output terminal under control of a voltage signal of the pull-up node;
a first pull-down control circuit configured to transmit a second clock signal to a pull-down node under control of the second clock signal;
a second pull-down control circuit configured to transmit a second voltage signal to the pull-down node under control of the voltage signal of the pull-up node;
a pull-up control circuit configured to transmit the second voltage signal to the pull-up node under control of a voltage signal of the pull-down node;
a pull-down circuit configured to transmit the second voltage signal to the signal output terminal under control of the voltage signal of the pull-down node; and
a holding circuit configured;
wherein an output signal of the signal output terminal of an M-th stage shift register unit is the first input signal of an (M+1)-th stage shift register unit;
wherein the holding circuit comprises at least one of a first holding unit and a second holding unit;
wherein the first holding unit is configured to transmit the second voltage signal to the pull-up node under control of the second input signal during a V-blank time period, the V-blank time period is a time period after a last stage of shift register unit outputs a high level signal in each frame;
wherein the second holding unit is configured to transmit the second input signal to the pull-down node under control of t

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Qin Wenwen
• Wang Zhen
• Sun Jian
• Zhan Xiaozhou
• Wang Jiguo
• Qiao Yun
• Huang Fei
• Zhang Han
• Wang Zhengkui
• Cong Lele

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title