Apparatus and methods for reduced computing device power consumption

Patent metadata

Field	Value
Publication number	US-10824216-B2
Application number	US-201816235600-A
Country	US
Kind code	B2
Filing date	Dec 28, 2018
Priority date	Dec 28, 2018
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

Methods, apparatus, systems and articles of manufacture are disclosed for reduced computing device power consumption. Example methods disclosed herein includes detecting frame updates corresponding to input frames to be presented by a display, causing a programmable timer to generate second interrupts corresponding to first interrupts generated by a display engine, the second interrupts to be generated when there are no frame updates detected for at least a first duration of time defined by a first threshold. Example methods further include causing the display engine to transition to a low power state when (1) the programmable timer is configured to generate the second interrupts and (2) no frame updates have been detected for at least a second duration of time following the first duration of time, the second duration of time defined by a second threshold.

First claim

What is claimed is:

1. An apparatus comprising:
a frame update tracker to detect frame updates corresponding to input frames to be presented by a display;
a software interrupt controller to cause a programmable timer to generate second interrupts corresponding to first interrupts generated by a display engine, the software interrupt controller to cause the programmable timer to generate the second interrupts when there are no frame updates detected for at least a first duration of time defined by a first threshold;
an interrupt masker to cause the first interrupts to be masked when (1) the second interrupts are being generated and (2) the display engine is not in a low power state; and
a display engine power controller to cause the display engine to transition to the low power state when (1) the programmable timer is configured to generate the second interrupts and (2) no frame updates have been detected for at least a second duration of time following the first duration of time, the second duration of time defined by a second threshold, at least one of the frame update tracker, the software interrupt controller, the interrupt masker or the display engine power controller implemented by at least one of hardware or at least one processor.

2. The apparatus of claim 1 , wherein the interrupt masker is to cause the first interrupts to be unmasked in response to the frame update tracker detecting a frame update while the first interrupts are masked.

3. The apparatus of claim 1 , further including an interrupt synchronizer to, in response to the frame update tracker detecting a frame update when the display engine is in the low power state:
determine an expected time of a next interrupt of the second interrupts;
access a power-on time for the display engine; and
cause the display engine to transition from the low power state to an operational state such that the display engine generates a startup interrupt of the first interrupts within a tolerance range of the expected time of the next interrupt of the second interrupts.

4. The apparatus of claim 3 , wherein in response to the display engine transitioning from the low power state to the operational state, the software interrupt controller causes the programmable timer to cease generating the second interrupts.

5. The apparatus of claim 1 , further including an interrupt synchronizer to cause the programmable timer to generate the second interrupts synchronized within a tolerance range of the first interrupts generated by the display engine.

6. The apparatus of claim 1 , wherein the first interrupts and the second interrupts include at least one of a vertical blanking interrupt, a VSYNC interrupt, a VBLANK interval, or a horizontal blanking interval.

7. The apparatus of claim 1 , wherein the first threshold corresponds to an amount of time for a specified number of input frames to be detected.

8. A non-transitory computer readable storage medium comprising computer readable instructions that, when executed, cause a processor to:
detect frame updates corresponding to input frames to be presented by a display;
cause a programmable timer to generate second interrupts corresponding to first interrupts generated by a display engine, the second interrupts to be generated when there are no frame updates detected for at least a first duration of time defined by a first threshold;
cause the first interrupts to be masked when (1) the second interrupts are being generated and (2) the display engine is not in a low power state; and
cause the display engine to transition to the low power state when (1) the programmable timer is configured to generate the second interrupts and (2) no frame updates have been detected for at least a second duration of time following the first duration of time, the second duration of time defined by a second threshold.

9. The non-transitory computer readable storage medium of claim 8 , wherein the instructions, when executed, cause the processor to cause the first interrupts to be unmasked in response to detection of a frame update while the first interrupts are masked.

10. The non-transitory computer readable storage medium of claim 8 , wherein the instructions, when executed, cause the processor to, in response to a frame update when the display engine is in the lower power state:
determine an expected time of a next interrupt of the second interrupts;
access a power-on time for the display engine; and
cause the display engine to transition from the low power state to an operational state such that the display engine generates a startup interrupt of the first interrupts within a tolerance range of the expected time of the next interrupt of the second interrupts.

11. The non-transitory computer readable storage medium of claim 10 , wherein the instructions, when executed, further cause the processor to, in response to the display engine transitioning from the low power state to the operational state, cause the programmable timer to cease generating the second interrupts.

12. The non-transitory computer readable storage medium of claim 8 , wherein the instructions, when executed, further cause the processor to cause the programmable timer to generate the second interrupts synchronized within a tolerance range of the first interrupts generated by the display engine.

13. The non-transitory computer readable storage medium of claim 8 , wherein the first interrupts and the second interrupts include at least one of a vertical blanking interrupt, a VSYNC interrupt, a VBLANK interrupt, or a horizontal blanking interval.

14. The non-transitory computer readable storage medium of claim 8 , wherein the first threshold corresponds to an amount of time for a specified number of input frames to be detected.

15. A method comprising:
detecting frame updates corresponding to input frames to be presented by a display;
causing a programmable timer to generate second interrupts corresponding to first interrupts generated by a display engine, the second interrupts to be generated when there are no frame updates detected for at least a first duration of time defined by a first threshold;
causing the first interrupts to be masked when (1) the second interrupts are being generated and (2) the display engine is not in a low power state; and
causing the display engine to transition to the low power state when (1) the programmable timer is configured to generate the second interrupts and (2) no frame updates have been detected for at least a second duration of time following the first duration of time, the second duration of time defined by a second threshold.

16. The method of claim 15 , further including causing the first interrupts to be unmasked in response to detecting a frame update while the first interrupts are masked.

17. The method of claim 15 , further including, in response to detecting a frame update when the display engine is in the low power state:
determining an expected time of a next interrupt of the second interrupts;
accessing a power-on time for the display engine; and
causing the display engine to transition from the low power state to an operational state such that the display engine generates a startup interrupt of the first interrupts within a tolerance range of the expected time of the next interrupt of the second interrupts.

Assignees

• Intel Corp

Inventors

• Diefenbaugh Paul
• Runyan Arthur
• Smith Gary
• Bui Kathy
• Saini Ajay
• Sinha Vishal
• Li Yifan
• Park Yong-Joon

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G06F1/3218 Primary

  of display devices · CPC title