Testing an integrated circuit receiver in a package using a varying analog voltage

Patent metadata

Field	Value
Publication number	US-10823780-B1
Application number	US-201816112433-A
Country	US
Kind code	B1
Filing date	Aug 24, 2018
Priority date	Aug 24, 2018
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

Examples herein describe techniques for testing a receiver interface on a die. In one embodiment, the die includes tester circuitry which includes a digital to analog convertor (DAC) which outputs an analog test signal to a selector circuit (e.g., a multiplexer) which forwards the analog test signal to a receiver. By varying the analog test signal, the tester circuitry can identify one or more trip points corresponding to the receiver. That is, by monitoring the output of the receiver, a testing application can determine when the output of the receiver switches states thereby indicating that the analog test signal at the input of the receiver corresponds to the trip point of the receiver. In this manner, internal circuitry (e.g., the tester circuitry) can be used to test a receiver interface that may otherwise be inaccessible.

First claim

What is claimed is:

1. A method for testing a first receiver in a semiconductor die, the method comprising:
selecting an analog voltage using a digital control signal transmitted to a digital to analog converter (DAC) in the semiconductor die;
transmitting the analog voltage from the DAC to a first multiplexer, wherein the first multiplexer forwards the analog voltage to the first receiver;
varying the analog voltage outputted by the DAC until an output of the first receiver changes states; and
recording a trip voltage of the first receiver, wherein the trip voltage corresponds to the analog voltage outputted by the DAC when the first receiver changes states.

2. The method of claim 1 , wherein varying the analog voltage outputted by the DAC comprises:
sweeping the analog voltage until the output of the first receiver changes states.

3. The method of claim 1 , wherein the semiconductor die is coupled to a memory die that sends data signals to the semiconductor die, wherein the method further comprises:
operating the semiconductor die in a normal operation mode during which the first multiplexer forwards the data signals transmitted by the memory die to the first receiver.

4. The method of claim 3 , wherein the semiconductor die is coupled to the memory die via an interposer, wherein a first I/O element couples the interposer to the memory die and a second I/O element couples the interposer to the first receiver in the semiconductor die.

5. The method of claim 3 , wherein the memory die is a high bandwidth memory (HBM).

6. The method of claim 3 , wherein a die-to-die communication interface between the memory die and the semiconductor die is inaccessible to general I/O elements for a package containing the memory die and the semiconductor die.

7. The method of claim 1 , wherein the DAC is coupled to a second multiplexer which is in turn coupled to a second receiver, the method further comprising:
transmitting the analog voltage from the DAC to the second multiplexer, wherein the second multiplexer forwards the analog voltage to the second receiver;
varying the analog voltage outputted by the DAC until an output of the second receiver changes states; and
recording a trip voltage of the second receiver, wherein the trip voltage corresponds to the analog voltage outputted by the DAC when the second receiver changes states.

8. The method of claim 7 , wherein the trip voltage of the first receiver is different from the trip voltage of the second receiver.

9. A semiconductor die, comprising:
a first multiplexer, wherein a first input of the first multiplexer is coupled to a receiver interface;
a DAC connected to a second input of the first multiplexer; and
a first receiver coupled to an output of the first multiplexer,
wherein the semiconductor die is configured to determine a trip point of the first receiver by:
selecting an analog voltage to output using the DAC,
transmitting the analog voltage from the DAC to the first multiplexer, wherein the first multiplexer forwards the analog voltage to the first receiver, and
varying the analog voltage outputted by the DAC until an output of the first receiver changes states.

10. The semiconductor die of claim 9 , wherein varying the analog voltage outputted by the DAC comprises:
sweeping the analog voltage until the output of the first receiver changes states.

11. The semiconductor die of claim 9 , wherein the receiver interface is configured to couple to a memory die that sends data signals to the semiconductor die via the receiver interface, wherein the semiconductor die is configured to:
operate in a normal operation mode during which the first multiplexer forwards the data signals transmitted by the memory die to the first receiver.

12. The semiconductor die of claim 11 , wherein the memory die is a high bandwidth memory (HBM).

13. The semiconductor die of claim 9 , further comprising:
a second multiplexer, wherein a first input of the second multiplexer is coupled to a second receiver interface and a second input of the second multiplexer is coupled to the DAC; and
a second receiver, wherein an output of the second multiplexer is coupled to the second receiver,
wherein the semiconductor die is configured to determine a trip point of the second receiver by:
transmitting the analog voltage from the DAC to the second multiplexer, wherein the second multiplexer forwards the analog voltage to the second receiver, and
varying the analog voltage outputted by the DAC until an output of the second receiver changes states.

14. A system, comprising:
a semiconductor die, comprising:
a first multiplexer coupled to a receiver interface,
a DAC connected to the first multiplexer, and
a first receiver coupled to the first multiplexer; and

a testing application communicatively coupled to the semiconductor die, wherein the testing application is configured to:
transmit a digital control signal that controls an analog voltage outputted using the DAC,
monitor an output of the first receiver to determine when the first receiver changes states, and
record a trip voltage of the first receiver, wherein the trip voltage corresponds to the analog voltage outputted by the DAC when the first receiver changes states.

15. The system of claim 14 , wherein the testing application is configured to:
transmit a plurality of digital control signals that cause the DAC to sweep the analog voltage until the first receiver changes states.

16. The system of claim 14 , further comprising:
a memory die that sends data signals to the semiconductor die during normal operation, wherein during normal operation mode the first multiplexer forwards the data signals transmitted by the memory die to the first receiver.

17. The system of claim 16 , further comprising:
an interposer coupling the semiconductor die to the memory die, wherein a first I/O element couples the interposer to the memory die and a second I/O element couples the interposer to the first receiver in the semiconductor die.

18. The system of claim 16 , wherein the memory die is a high bandwidth memory (HBM).

19. The system of claim 16 , wherein a die-to-die communication interface between the memory die and the semiconductor die is inaccessible to general I/O elements for a package containing the memory die and the semiconductor die.

20. The system of claim 14 , wherein the DAC is coupled to a second multiplexer which is in turn coupled to a second receiver in the semiconductor die,
wherein the testing application is configured to:
monitor an output of the second receiver to determine when the second receiver changes states, and
record a trip voltage of the second receiver, wherein the trip voltage corresponds to the analog voltage outputted by the DAC when the second receiver changes states.

Assignees

• Xilinx Inc

Inventors

• Tabalujan Andrew
• Wang Xiaobao
• Huang Gubo

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H04B17/201

  for measurement of specific parameters of the receiver or components thereof · CPC title

• G01R31/318513 Primary

  Test of Multi-Chip-Moduls · CPC title