Inverter-based successive approximation capacitance-to-digital converter

Patent metadata

Field	Value
Publication number	US-10819359-B2
Application number	US-201615760456-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Sep 17, 2015
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog-to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter-based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.

First claim

What is claimed is:

1. An apparatus for capacitance-to-digital conversion, the apparatus comprising:
first and second sensor capacitors configured to produce an input capacitance;
first and second capacitive digital-to-analog converters (CapDACs) configured to produce a reference capacitance;
an inverter-based operational transconductance amplifier, OTA, circuits connected to the first and second sensor capacitors and to the first and second CapDACs and configured to amplify a difference between the input capacitance and the reference capacitance or a scaled or shifted version of the input capacitance and the reference capacitance;
a comparator connected to the inverter-based OTA; and
successive approximation register (SAR) logic circuitry connected between the comparator and the first and second CapDACs, and configured to, with the first and second CapDACs, the inverter-based OTA, and the comparator, produce a digital signal representative of the input capacitance.

2. The apparatus of claim 1 , wherein the comparator is a latch comparator configured to receive an amplified signal from the inverter-based OTA and output a strengthened signal to the SAR logic circuitry.

3. The apparatus of claim 1 , wherein the inverter-based OTA comprises a simple inverter, a current-starved inverter, a cascode inverter, or a fully differential cascode inverter.

4. The apparatus of claim 1 , wherein the inverter-based OTA comprises a single ended input single ended output circuit, a differential input single ended output circuit, or a differential input differential output circuit.

5. The apparatus of claim 1 , wherein inverter-based OTA comprise a fully differential configuration that is insensitive to common mode noise and common mode errors.

6. The apparatus of claim 1 , wherein the inverter-based OTA is selectively enabled to provide constant energy consumption and energy efficiency independent of the sample rate.

7. The apparatus of claim 1 , wherein auto-calibration is used by measuring one or more reference capacitors to cancel or reduce conversion errors.

8. The apparatus of claim 1 , wherein one or more reference voltages is digitally controlled to increase the capacitance range or improve the absolute resolution.

9. The apparatus of claim 1 , wherein each of the first and second CapDACs comprises a coarse-fine design which allows a wide capacitance range and fine absolute resolution.

10. The apparatus of claim 1 , wherein at least one unit capacitor of the first and second CapDACs comprises an integrated capacitor.

11. The apparatus of claim 10 , wherein the integrated capacitor comprises a poly-insulator poly (PIP) capacitor, a metal-insulator-metal (MIM) capacitor, a dual MIM (DMIM) capacitor, or a metal-oxide-metal (MOM) capacitor.

12. The apparatus of claim 1 , further comprising:
a fine conversion stage element configured to
perform capacitance-to-digital conversion; and
generate a residual error between the input capacitance and the reference capacitance.

13. The apparatus of claim 12 , wherein the fine conversion stage element comprises a capacitance-to-digital converter.

14. The apparatus of claim 13 , wherein the fine conversion stage element comprises an integrating converter or a sigma-delta converter.

15. A method for capacitance-to-digital conversion, the method comprising:
producing, by first and second sensor capacitors, an input capacitance;
producing, by first and second capacitive digital-to-analog converters (CapDACs), a reference capacitance;
amplifying, by an inverter-based operational transconductance amplifier, OTA, connected to the first and second sensor capacitors and to the first and second CapDACs, a difference between the input capacitance and the reference capacitance or a scaled or shifted version of the input capacitance and the reference capacitance;
comparing amplified signals from the inverter-based OTA and outputting a strengthened signal; and
producing, by successive approximation register (SAR) logic circuitry, which is connected between the comparator and the first and second CapDACs, and with the first and second CapDACs, the inverter-based OTA, and the comparator, a digital signal representative of the input capacitance.

16. The method of claim 15 ,
wherein the inverter-based OTA is a latch comparator.

17. The method of claim 15 ,
wherein the inverter-based OTA comprises a simple inverter, a current-starved inverter, a cascode inverter, or a fully differential cascode inverter, or
wherein the inverter-based OTA comprises a single ended input single ended output circuit, a differential input single ended output circuit, or a differential input differential output circuit, or
wherein the inverter-based OTA comprises a fully differential configuration that is insensitive to common mode noise and common mode errors, or
wherein the inverter-based OTA is selectively enabled to provide constant energy consumption and energy efficiency independent of the sample rate.

18. The method of claim 15 , further comprising using auto-calibration by measuring one or more reference capacitors to cancel or reduce conversion errors.

19. The method of claim 15 , further comprising digitally controlling one or more reference voltages to increase the capacitance range or improve the absolute resolution.

20. The method of claim 15 , further comprising:
performing, by a fine conversion stage element, capacitance-to-digital conversion; and
generating, by the fine conversion stage element, a residual error between the input capacitance and the reference capacitance.

Assignees

• Univ King Abdullah Sci & Tech

Inventors

• Omran Hesham
• Alhoshany Abdulaziz
• Salama Khaled

Classifications

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• G01D5/24 Primary

  by varying capacitance · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/42

  Sequential comparisons in series-connected stages with no change in value of analogue signal · CPC title