Timing controller resetting circuit and a display device including the same

Patent metadata

Field	Value
Publication number	US-10819333-B2
Application number	US-201916260346-A
Country	US
Kind code	B2
Filing date	Jan 29, 2019
Priority date	Feb 14, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A timing controller resetting circuit including: a resistor connected to an output node from which a reset signal is output and a first voltage source which supplies a first voltage; a capacitor connected to the output node and a second voltage source which supplies a second voltage that is lower than the first voltage; a reference voltage source configured to generate a reference voltage that is lower than the first voltage and higher than the second voltage; a comparator including a first input terminal which receives the first voltage, a second input terminal which receives the reference voltage, and an output terminal which outputs a comparison result signal generated by comparing the first voltage with the reference voltage; and a transistor including a first terminal which is connected to the output node, a second terminal which receives the second voltage, and a gate terminal which receives the comparison result signal.

First claim

What is claimed is:

1. A timing controller resetting circuit, comprising:
a resistor connected to an output node from which a reset signal is output and a first voltage source which supplies a first voltage;
a capacitor connected to the output node and a second voltage source which supplies a second voltage that is lower than the first voltage;
a reference voltage source configured to generate a reference voltage that is lower than the first voltage and higher than the second voltage;
a comparator including a first input terminal which receives the first voltage, a second input terminal which receives the reference voltage, and an output terminal which outputs a comparison result signal generated by comparing the first voltage with the reference voltage; and
a transistor including a first terminal which is connected to the output node, a second terminal which receives the second voltage which is a ground voltage and is connected to the capacitor, and a gate terminal which receives the comparison result signal.

2. The timing controller resetting circuit of claim 1 , wherein the first voltage is a source voltage which is supplied from a power source, and the second voltage is the ground voltage which is supplied from a ground source.

3. The timing controller resetting circuit of claim 1 , wherein the first input terminal of the comparator is a negative input terminal, the second input terminal of the comparator is a positive input terminal, and the transistor is an n-channel metal oxide semiconductor (NMOS) transistor.

4. The timing controller resetting circuit of claim 3 , wherein the comparison result signal has a low voltage level when the first voltage is higher than the reference voltage, and the transistor is turned off when the comparison result signal has the low voltage level.

5. The timing controller resetting circuit of claim 3 , wherein the comparison result signal has a high voltage level when the first voltage is lower than the reference voltage, and the transistor is turned on when the comparison result signal has the high voltage level.

6. The timing controller resetting circuit of claim 1 , wherein the first input terminal of the comparator is a positive input terminal, the second input terminal of the comparator is a negative input terminal, and the transistor is a p-channel metal oxide semiconductor (PMOS) transistor.

7. The timing controller resetting circuit of claim 6 , wherein the comparison result signal has a high voltage level when the first voltage is higher than the reference voltage, and the transistor is turned off when the comparison result signal has the high voltage level.

8. The timing controller resetting circuit of claim 6 , wherein the comparison result signal has a low voltage level when the first voltage is lower than the reference voltage, and the transistor is turned on when the comparison result signal has the low voltage level.

9. A timing controller resetting circuit, comprising:
a resistor connected to an output node from which a reset signal is output and a first voltage source which supplies a first voltage;
a capacitor connected to the output node and a second voltage source which supplies a second voltage that is lower than the first voltage;
a comparator including a first input terminal which receives the first voltage, a second input terminal which receives a reference voltage that is lower than the first voltage and higher than the second voltage, and an output terminal which outputs a comparison result signal generated by comparing the first voltage with the reference voltage; and
a transistor including a first terminal which is connected to the output node, a second terminal which is connected to the capacitor and which receives the second voltage which is a ground voltage, and a gate terminal which receives the comparison result signal.

10. The timing controller resetting circuit of claim 9 , wherein the first voltage is a source voltage which is supplied from a power source, and the second voltage is the ground voltage which is supplied from a ground source.

11. The timing controller resetting circuit of claim 9 , wherein the first input terminal of the comparator is a negative input terminal, the second input terminal of the comparator is a positive input terminal, and the transistor is an n-channel metal oxide semiconductor (NMOS) transistor.

12. The timing controller resetting circuit of claim 11 , wherein the comparison result signal has a low voltage level when the first voltage is higher than the reference voltage, and the transistor is turned off when the comparison result signal has the low voltage level.

13. The timing controller resetting circuit of claim 11 , wherein the comparison result signal has a high voltage level when the first voltage is lower than the reference voltage, and the transistor is turned on when the comparison result signal has the high voltage level.

14. The timing controller resetting circuit of claim 9 , wherein the first input terminal of the comparator is a positive input terminal, the second input terminal of the comparator is a negative input terminal, and the transistor is a p-channel metal oxide semiconductor (PMOS) transistor.

15. The timing controller resetting circuit of claim 14 , wherein the comparison result signal has a high voltage level when the first voltage is higher than the reference voltage, and the transistor is turned off when the comparison result signal has the high voltage level.

16. The timing controller resetting circuit of claim 14 , wherein the comparison result signal has a low voltage level when the first voltage is lower than the reference voltage, and the transistor is turned on when the comparison result signal has the low voltage level.

17. A display device, comprising:
a display panel including a plurality of pixel circuits;
a scan driver configured to provide a scan signal to the pixel circuits;
a data driver configured to provide a data signal to the pixel circuits;
a timing controller configured to control the scan driver and the data driver and to operate based on a reset signal; and
a timing controller resetting circuit configured to receive a source voltage output from a power source and to generate the reset signal based on the source voltage,
wherein the timing controller operates after the reset signal switches from a low voltage level to a high voltage level as the power source is turned on,
wherein the timing controller does not operate after the reset signal switches from the high voltage level to the low voltage level as the power source is turned off,
wherein the timing controller resetting circuit drops the reset signal to the low voltage level when the source voltage becomes lower than a reference voltage as the power source is turned off,
wherein the timing controller resetting circuit maintains the reset signal to have the low voltage level before the source voltage becomes higher than the reference voltage as the power source is turned on, and
wherein the timing controller resetting circuit comprises:
a resistor connected to an output node from which the reset signal is output and the power source;
a capacitor connected to the output node and a ground source which supplies a ground voltage;
a comparator including a first input terminal which receives the source voltage, a second input terminal which receives the reference voltage, and an output terminal which outputs a comparison result signal generated by comparing the source voltage with the reference voltage; and
a transistor including a first terminal which is connec

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Ga-Na
• Park Po-Yun
• Kim Hong-Kyu
• Kim Myeongsu
• Park Dongwon

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• H03K17/22 Primary

  Modifications for ensuring a predetermined initial state when the supply voltage has been applied (bi-stable generators H03K3/12) · CPC title