Method for minimizing distortion of a signal in a radiofrequency circuit

Patent metadata

Field	Value
Publication number	US-10819282-B2
Application number	US-201816614732-A
Country	US
Kind code	B2
Filing date	May 23, 2018
Priority date	May 23, 2017
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.

First claim

The invention claimed is:

1. A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of an input or output signal exhibits a trough around a given power (P Dip ), the method comprising applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (V GB ) chosen so as to move the trough toward an operating power of the radiofrequency circuit.

2. The method of claim 1 , wherein the electrical potential difference (V GB ) is chosen so as to comply with the following equation: V pk =|V GB −V FB |, where V pk is the peak voltage of the radiofrequency signal and V FB is the flat band voltage.

3. The method of claim 1 , wherein the semiconductor substrate has an electrical resistivity of greater than 500 Ω·cm.

4. The method of claim 3 , wherein a polycrystalline silicon layer is disposed between the semiconductor substrate and the electrically insulating layer.

5. The method of claim 4 , wherein an additional electrically insulating layer is disposed between the semiconductor substrate and the polycrystalline silicon layer.

6. The method of claim 1 , wherein the semiconductor substrate comprises silicon.

7. The method of claim 1 , further comprising adjusting the electrical potential difference (V GB ) applied between the semiconductor substrate and the radiofrequency circuit depending on the operating power of the radiofrequency circuit.

8. The method of claim 1 , further comprising measuring a temperature of the radiofrequency circuit, and adjusting the electrical potential difference (V GB ) applied between the semiconductor substrate and the radiofrequency circuit depending on the measured temperature.

9. The method of claim 1 , wherein the curve representing the distortion of the signal is a curve of the level of generation of a second or of a third harmonic of the input signal or of the output signal as a function of the power of the input signal or of a fundamental component of the output signal.

10. A radiofrequency device, comprising:
a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer;
a contact connected electrically to the semiconductor substrate;
a device configured to apply a potential difference (V GB ) between the contact and the radiofrequency circuit, the potential difference (V GB ) selected so as to move a trough around a given power (P Dip ) in a curve representing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in the circuit as a function of a power of the input or output signal toward an operating power of the radiofrequency circuit.

11. The device of claim 10 , wherein the device configured to apply the potential difference (V GB ) comprises a voltage generator and a voltage control module configured to adjust the voltage of the generator depending on the operating power of the radiofrequency circuit.

12. The device of claim 11 , wherein the semiconductor substrate has an electrical resistivity of greater than 500 Ω·cm.

13. The device of claim 12 , further comprising a polycrystalline silicon layer disposed between the semiconductor substrate and the electrically insulating layer.

14. The device of claim 13 , further comprising an additional electrically insulating layer disposed between the semiconductor substrate and the polycrystalline silicon layer.

15. The device of claim 14 , wherein the semiconductor substrate comprises silicon.

16. The device of claim 15 , further comprising a temperature sensor coupled to the device configured to apply the potential difference (V GB ), the device configured to apply the potential difference (V GB ) being configured to adjust the potential difference depending on the temperature measured by the sensor.

17. The device of claim 15 , further comprising a temperature sensor coupled to the device configured to apply the potential difference (V GB ), the device configured to apply the potential difference (V GB ) being configured to adjust the potential difference depending on the temperature measured by the sensor.

18. The device of claim 10 , wherein the semiconductor substrate has an electrical resistivity of greater than 500 Ω·cm.

19. The device of claim 18 , further comprising a polycrystalline silicon layer disposed between the semiconductor substrate and the electrically insulating layer.

20. The device of claim 10 , wherein the semiconductor substrate comprises silicon.

Assignees

• Soitec Silicon On Insulator

Inventors

• Broekaart Marcel
• Allibert Frederic
• Desbonnets Eric
• Raskin Jean-Pierre
• Rack Martin

Classifications

• H10W44/241

  for passive devices or passive elements · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906 Primary

  Preparing SOI wafers · CPC title

• H03C7/00 Primary

  Modulating electromagnetic waves (devices or arrangements for the modulation of light G02F1/00) · CPC title