Oscillator circuit

Patent metadata

Field	Value
Publication number	US-10819277-B2
Application number	US-201916527471-A
Country	US
Kind code	B2
Filing date	Jul 31, 2019
Priority date	Jul 31, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A differential Colpitts oscillator circuit is described which provides a larger tuning range, has better phase noise and uses less power than conventional differential Colpitts oscillator circuits. The circuit is characterized by a capacitive ladder in which only variable capacitor is used for tuning the circuit. In some embodiments, a variable capacitor can be used for fine tuning.

First claim

What is claimed is:

1. A circuit comprising:
a first transistor and a second transistor;
a first inductor connected in a first line between a first gate of the first transistor and a connecting point;
a third transistor and a fourth transistor;
a second inductor connected in a second line between a second gate of the third transistor and the connecting point;
a first pair of capacitors connected between the first gate and a first source of the first transistor;
a second pair of capacitors connected between the second gate and a second source of the third transistor; and
a variable capacitor connected to the first pair of capacitors and the second pair of capacitors,
wherein a fourth gate of the fourth transistor is connected to a first center-tap point of the first inductor and a third gate of the second transistor is connected to a second center-tap point of the second inductor.

2. The circuit according to claim 1 , the variable capacitor being adjustable to adjust a tuning range of the circuit.

3. A circuit comprising:
a first transistor comprising a first terminal and a second terminal that is a gate terminal;
a second transistor comprising a third terminal and a fourth terminal;
a third transistor comprising a fifth terminal and a sixth terminal that is a gate terminal;
a fourth transistor comprising a seventh terminal and an eighth terminal;
a first inductor comprising a ninth terminal and a tenth terminal;
a second inductor comprising an eleventh terminal and a twelfth terminal;
a resistor comprising a thirteenth terminal; and
a capacitive ladder comprising a fourteenth terminal, a fifteenth terminal, a sixteenth terminal, and a seventeenth terminal,
wherein the second terminal, the fifteenth terminal, and the ninth terminal form a first node,
wherein the tenth terminal and the eleventh terminal form a second node,
wherein the twelfth terminal, the seventeenth terminal, and the sixth terminal form a third node,
wherein the first terminal, the fourteenth terminal, and the third terminal form a fourth node,
wherein the fifth terminal, the sixteenth terminal, and the seventh terminal form a fifth node, and
wherein the fourth terminal, the eighth terminal, and the thirteenth terminal form a sixth node,
wherein the capacitive ladder comprises:
a first capacitor comprising an eighteenth terminal;
a second capacitor comprising a nineteenth terminal;
a third variable capacitor comprising a twentieth terminal and a twenty-first terminal;
a fourth capacitor comprising a twenty-second terminal; and
a fifth capacitor comprising a twenty-third terminal,
wherein the eighteenth terminal, the nineteenth terminal, and the twentieth terminal form a seventh node, and
wherein the twenty-first terminal, the twenty-second terminal, and the twenty-third terminal form an eighth node.

4. The circuit according to claim 3 , further comprising a sixth variable capacitor comprising a twenty-fourth terminal and a twenty-fifth terminal, wherein the twenty-fourth terminal additionally forms the fourth node, and wherein the twenty-fifth terminal additionally forms the fifth node.

5. The circuit according to claim 4 ,
wherein the first inductor further comprises a first center-tap terminal,
wherein the second inductor further comprises a second center-tap terminal,
wherein the second transistor further comprises a twenty-sixth terminal that is a gate terminal,
wherein the fourth transistor further comprises a twenty-seventh terminal that is a gate terminal,
wherein the twenty-seventh terminal and the first center-tap terminal form a ninth node, and
wherein the twenty-sixth terminal and the second center-tap terminal form a tenth node.

6. The circuit according to claim 5 , wherein the sixth variable capacitor is adjustable to adjust a tuning range of the circuit.

7. The circuit according to claim 5 , wherein the third variable capacitor is adjustable to adjust a tuning range of the circuit.

Assignees

• Stichting Imec Nederland
• Stitching Imec Nederland

Inventors

• Zhou Cui
• Mateman Paul

Classifications

• H03B2200/009

  Reduction of phase noise · CPC title

• H03B5/1218

  the generator being of the balanced type · CPC title

• H03B2200/004

  including a variable capacitance, e.g. a varicap, a varactor or a variable capacitance of a diode or transistor · CPC title

• H03B2200/0008

  Colpitts oscillator · CPC title

• H03B5/124

  the means comprising a voltage dependent capacitance · CPC title