TFT substrate, scanned antenna having TFT substrate, and method for manufacturing TFT substrate

Patent metadata

Field	Value
Publication number	US-10819006-B2
Application number	US-201916259803-A
Country	US
Kind code	B2
Filing date	Jan 28, 2019
Priority date	Jan 30, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A TFT substrate has a semiconductor layer, a gate metal layer including a gate electrode, a gate insulating layer, a source metal layer including a source electrode and a drain electrode, and a contact layer including a source contact portion and a drain contact portion. The source metal layer has a laminated structure including a lower source metal layer and an upper source metal layer, and an edge of the lower source metal layer is positioned inside an edge of the upper source metal layer. At least a portion, which does not overlap the source contact portion or the drain contact portion in the edge of the lower source metal layer and the edge of the upper source metal layer in the plurality of antenna unit regions when viewed in a direction normal to the dielectric substrate, is covered with at least two inorganic layers.

First claim

What is claimed is:

1. A TFT substrate including a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate and each having a TFT and a patch electrode electrically connected to a drain electrode of the TFT, the TFT substrate comprising:
a semiconductor layer of the TFT;
a gate metal layer including a gate electrode of the TFT;
a gate insulating layer formed between the gate metal layer and the semiconductor layer;
a source metal layer formed on the semiconductor layer and including a source electrode and the drain electrode electrically connected to the semiconductor layer; and
a contact layer including a source contact portion formed between the semiconductor layer and the source electrode and a drain contact portion formed between the semiconductor layer and the drain electrode,
wherein the source metal layer has a laminated structure including a lower source metal layer including at least one element selected from a group consisting of Ti, Ta, and W, and an upper source metal layer formed on the lower source metal layer and including Cu or Al,
an edge of the lower source metal layer is positioned inside an edge of the upper source metal layer when viewed in a direction normal to the dielectric substrate,
at least a portion of the edge of the lower source metal layer in the plurality of antenna unit regions, which does not overlap the source contact portion or the drain contact portion, and a portion of the edge of the upper source metal layer in the plurality of antenna unit regions, which does not overlap the source contact portion or the drain contact portion, are covered with at least two inorganic layers, when viewed in the direction normal to the dielectric substrate, and
a side surface of the lower source metal layer is exposed from the upper source metal layer.

2. The TFT substrate according to claim 1 ,
wherein the entire edge of the lower source metal layer and the entire edge of the upper source metal layer in the plurality of antenna unit regions are covered with the at least two inorganic layers when viewed in the direction normal to the dielectric substrate.

3. The TFT substrate according to claim 1 ,
wherein the semiconductor layer is positioned above the gate electrode,
the TFT substrate further includes an interlayer insulating layer covering the TFT and an upper conductive layer formed on the interlayer insulating layer, and
the at least two inorganic layers include the interlayer insulating layer and the upper conductive layer.

4. The TFT substrate according to claim 3 ,
wherein the source metal layer further includes the patch electrode.

5. The TFT substrate according to claim 3 ,
wherein the upper conductive layer includes a transparent conductive layer.

6. The TFT substrate according to claim 3 ,
wherein the upper conductive layer includes a first layer including a transparent conductive layer and a second layer formed under the first layer and which is formed from at least one layer selected from a group consisting of a Ti layer, a MoNb layer, a MoNbNi layer, a MoW layer, a W layer, and a Ta layer.

7. The TFT substrate according to claim 3 , further comprising:
a terminal portion arranged in a region other than the plurality of antenna unit regions,
wherein the terminal portion has a lower connection portion included in the gate metal layer, a contact hole formed in the gate insulating layer and the interlayer insulating layer and reaching the lower connection portion, and an upper connection portion included in the upper conductive layer and connected to the lower connection portion in the contact hole.

8. The TFT substrate according to claim 3 ,
wherein the upper conductive layer is formed to cover at least a portion which does not overlap the source contact portion or the drain contact portion in the edge of the lower source metal layer and the edge of the upper source metal layer in the plurality of antenna unit regions when viewed in the direction normal to the dielectric substrate.

9. The TFT substrate according to claim 3 ,
wherein the upper conductive layer is formed to cover the entire edge of the lower source metal layer and the entire edge of the upper source metal layer in the plurality of antenna unit regions when viewed in the direction normal to the dielectric substrate.

10. The TFT substrate according to claim 3 ,
wherein the upper conductive layer is formed to cover the entire lower source metal layer and the entire upper source metal layer in the plurality of antenna unit regions when viewed in the direction normal to the dielectric substrate.

11. The TFT substrate according to claim 1 ,
wherein the gate electrode is positioned above the source electrode and the drain electrode,
the TFT substrate further includes an interlayer insulating layer covering the TFT, a first upper conductive layer formed on the interlayer insulating layer, and a second upper conductive layer formed on the first upper conductive layer, and
the at least two inorganic layers include any one of the gate insulating layer, the interlayer insulating layer, the first upper conductive layer, and the second upper conductive layer.

12. The TFT substrate according to claim 11 ,
wherein the source metal layer further includes the patch electrode.

13. The TFT substrate according to claim 12 ,
wherein the edge of the lower source metal layer of the patch electrode and the edge of the upper source metal layer of the patch electrode are covered with the first upper conductive layer and the second upper conductive layer when viewed in the direction normal to the dielectric substrate.

14. The TFT substrate according to claim 12 ,
wherein a first contact hole reaching the patch electrode is formed in the gate insulating layer and the interlayer insulating layer, and
the first upper conductive layer and/or the second upper conductive layer cover the patch electrode exposed in the first contact hole.

15. The TFT substrate according to claim 11 ,
wherein the first upper conductive layer and the second upper conductive layer each include a transparent conductive layer.

16. The TFT substrate according to claim 11 ,
wherein the second upper conductive layer includes a first layer including a transparent conductive layer and a second layer formed under the first layer and which is formed from at least one layer selected from a group consisting of a Ti layer, a MoNb layer, a MoNbNi layer, a MoW layer, a W layer, and a Ta layer.

17. The TFT substrate according to claim 11 , further comprising:
a terminal portion arranged in a region other than the plurality of antenna unit regions,
wherein the terminal portion has a lower connection portion included in the source metal layer, a second contact hole formed in the gate insulating layer and the interlayer insulating layer and reaching the lower connection portion, and an upper connection portion included in the first upper conductive layer and/or the second upper conductive layer and connected to the lower connection portion in the second contact hole.

18. A scanning antenna comprising:
the TFT substrate according to claim 1 ;
a slot substrate arranged to face the TFT substrate;
a liquid crystal layer provided between the TFT substrate and the slot substrate; and
a reflective conductive plate arranged to face a surface of the slot substrate on an opposite side to the liquid crystal layer with a dielectric layer interposed therebetween,
wherein the slot substrate has another dielectric substrate, and a slot electrode f

Assignees

• Sharp Kk

Inventors

• Misaki Katsunori

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title