Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10818747-B2
Application number	US-201916407916-A
Country	US
Kind code	B2
Filing date	May 9, 2019
Priority date	Jun 4, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A semiconductor device capable of lowering a temperature coefficient and increasing a sheet resistance value (ρs value) and a manufacturing method thereof are provided. The resistive layer RL is made of polycrystalline silicon containing boron. The concentration distribution of boron in the thickness direction of the resistive layer RL includes a concentration peak PC and a low concentration portion LC having a concentration of boron lower than the concentration of boron in the concentration peak PC by two orders of magnitude or more.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first conductive layer; a second conductive layer; and a resistive layer having a first end and a second end connected to the first conductive layer at the first end, the resistive layer being connected to the second conductive layer at the second end,
wherein the resistive layer is comprised of polycrystalline silicon comprising p-type impurities without comprising n-type impurities, and
wherein a concentration distribution of the p-type impurities in a thickness direction of the resistive layer comprises:
a concentration peak; and
a low concentration portion having a concentration of the p-type impurities less than a concentration of the p-type impurities at the concentration peak by two orders of magnitude,

wherein the concentration peak and the low concentration portion are located at a central portion of the resistive layer, the central portion being between the first end and the second end.

2. The semiconductor device according to claim 1 ,
wherein the resistive layer has:
a lower surface; and
an upper surface facing the lower surface in the thickness direction, and

wherein the concentration peak is located within a range of ⅓ of a thickness of the resistive layer from the upper surface.

3. The semiconductor device according to claim 2 ,
wherein a portion in which the concentration of the p-type impurities is less than the concentration of the p-type impurities of the concentration peak by two orders of magnitude, is located within a range of ⅘ of the thickness of the resistive layer from the upper surface.

4. The semiconductor device according to claim 1 ,
wherein the resistive layer has:
a lower surface; and
an upper surface facing the lower surface in the thickness direction, and

wherein the resistive layer has:
a first layer; and
a second layer in contact with a surface of the first layer in an upper surface side, and

wherein a plurality of crystal grains in the first layer and a plurality of crystal grains in the second layer are separated with each other at a boundary between the first layer and the second layer.

5. The semiconductor device of claim 4 ,
wherein the concentration peak is located in the second layer.

6. The semiconductor device according to claim 1 ,
wherein the p-type impurities contain boron.

7. A method of manufacturing a semiconductor device, comprising:
forming a resistive layer comprised of polycrystalline silicon, the resistive layer having a first end and a second end; and
forming a first conductive layer connected to the resistive layer at the first end, and forming a second conductive layer connected to the resistive layer at the second end,
wherein the forming the resistive layer comprises:
forming the resistive layer comprising p-type impurities without comprising n-type impurities;
forming a film composed of the resistive layer:
introducing the p-type impurities into the resistive layer; and
annealing the resistive layer to activate the p-type impurities introduced into the resistive layer,

wherein a concentration distribution of p-type impurities in a thickness direction of the resistive layer comprises:
a concentration peak; and
a low concentration portion having a concentration of the p-type impurities less than a concentration of p-type impurities at the concentration peak by two orders of magnitude, and

wherein the concentration peak and the low concentration portion are located at a central portion of the resistive layer, the central portion being between the first end and the second end.

8. The method of manufacturing a semiconductor device according to claim 7 ,
wherein the resistive layer has:
a lower surface; and
an upper surface facing the lower surface in the thickness direction, and

wherein the introducing the p-type impurities into the resistive layer is performed so that the concentration peak is located within a range of ⅓ of a thickness of the resistive layer from the upper surface.

9. The method of manufacturing a semiconductor device according to claim 8 ,
wherein the introducing the p-type impurities into the resistive layer and the annealing the resistive layer are performed so that a portion having a concentration of the p-type impurities which is less than the concentration of the p-type impurities in the concentration peak by two orders of magnitude is located within a range of ⅘ of the thickness of the resistive layer from the upper surface.

10. The method of manufacturing a semiconductor device according to claim 7 ,
wherein the p-type impurities contain boron.

11. The method of manufacturing a semiconductor device according to claim 7 ,
wherein the resistive layer has:
a lower surface; and
an upper surface opposed to the lower surface in the thickness direction, and

wherein the forming the resistive layer includes:
forming a first layer; and
forming a second layer being in contact with a surface of the first layer on an upper surface side, and

wherein the first layer and the second layer are formed so that a plurality of crystal grains in the first layer and the plurality of crystal grains in the second layer are separated from each other at a boundary between the first layer and the second layer.

12. The method of manufacturing a semiconductor device according to claim 11 ,
wherein the introducing the p-type impurities into the resistive layer is performed so that the concentration peak is located in the second layer.

13. The method of manufacturing a semiconductor device according to claim 12 ,
wherein the p-type impurities contain boron.

14. The method of manufacturing a semiconductor device according to claim 10 ,
wherein, in the introducing the p-type impurities into the resistive layer, the p-type impurities are introduced into the resistive layer by injecting boron fluoride into the resistive layer.

15. The method of manufacturing a semiconductor device according to claim 13 ,
wherein, in the introducing the p-type impurities into the resistive layer, the p-type impurities are introduced into the resistive layer by injecting boron fluoride into the resistive layer.

Assignees

• Renesas Electronics Corp

Inventors

• Kodama Eisuke

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title