Semiconductor device

Patent metadata

Field	Value
Publication number	US-10818630-B2
Application number	US-201616347368-A
Country	US
Kind code	B2
Filing date	Nov 21, 2016
Priority date	Nov 21, 2016
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

An object of the present invention is to provide a highly reliable semiconductor device that allows voids remaining in a bonding material to be reduced. The semiconductor device includes a semiconductor chip, an insulation substrate, a metal base plate, a resin section, and a bump. The semiconductor chip is warped into a concave shape. On the insulation substrate, the semiconductor chip is mounted by bonding. The metal base plate has the insulation substrate mounted thereon and has a heat dissipation property. The resin section seals the insulation substrate and the semiconductor chip. The bump is disposed in a joint between the semiconductor chip and the insulation substrate. A warp amount of the semiconductor chip warped into a concave shape is equal to or greater than 1 μm and less than a height of the bump.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor chip warped into a concave shape;
an insulation substrate on which the semiconductor chip is mounted by bonding;
a base plate on which the insulation substrate is mounted, the base plate having a heat dissipation property;
a resin section that seals the insulation substrate and the semiconductor chip; and
a bump disposed in a joint between the semiconductor chip and the insulation substrate, wherein
a warp amount of the semiconductor chip warped into a concave shape is equal to or greater than 1 μm and less than a height of the bump.

2. A semiconductor device comprising:
a semiconductor chip warped into a concave shape;
an insulation substrate on which the semiconductor chip is mounted by bonding;
a base plate on which the insulation substrate is mounted, the base plate having a heat dissipation property;
a resin section that seals the insulation substrate and the semiconductor chip;
an upper electrode provided on an upper surface of the semiconductor chip; and
a lead frame bonded to the upper electrode.

3. The semiconductor device according to claim 2 , wherein
the bump is disposed in a joint between the semiconductor chip and the insulation substrate.

4. The semiconductor device according to claim 1 , wherein
a thickness of the semiconductor chip is equal to or less than 100 μm.

5. The semiconductor device according to claim 1 , further comprising:
a lower electrode provided on a lower surface of the semiconductor chip; and
an upper electrode provided on an upper surface of the semiconductor chip, the upper electrode having a linear expansion coefficient greater than a linear expansion coefficient of the lower electrode.

6. The semiconductor device according to claim 1 , further comprising:
a lower electrode provided on a lower surface of the semiconductor chip; and
an upper electrode provided on an upper surface of the semiconductor chip, the upper electrode being thicker than the lower electrode.

7. The semiconductor device according to claim 1 , further comprising a
thermosetting resin layer provided on an upper surface of the semiconductor chip, the thermosetting resin layer having a linear expansion coefficient greater than a linear expansion coefficient of the semiconductor chip.

8. The semiconductor device according to claim 2 , further comprising a thermosetting resin layer provided in a region on the upper surface of the semiconductor chip where the upper electrodes is not provided, the thermosetting resin layer having a linear expansion coefficient greater than a linear expansion coefficient of the semiconductor chip.

9. The semiconductor device according to claim 7 , wherein
the thermosetting resin layer is formed in a linear shape extending in one direction along the upper surface of the semiconductor chip.

10. The semiconductor device according to claim 2 , wherein
a thickness of the semiconductor chip is equal to or less than 100 μm.

11. The semiconductor device according to claim 8 , wherein
the thermosetting resin layer is formed in a linear shape extending in one direction along the upper surface of the semiconductor chip.

Assignees

• Mitsubishi Electric Corp

Inventors

• Yoshioka Yuki
• Sasaki Taishi
• Harada Hiroyuki

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/865

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/90

  Bond pads, in general · CPC title