Shift register circuit and driving method thereof, gate driver on array circuit, and touch sensing display panel

Patent metadata

Field	Value
Publication number	US-10818255-B2
Application number	US-201715761342-A
Country	US
Kind code	B2
Filing date	Apr 13, 2017
Priority date	Apr 13, 2017
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A shift register circuit including a switch control port configured to couple to a pull-up node via two transistors in series controlled by another transistor. The switch control port is configured to keep at a low voltage level during a display scan stage for the shift register circuit to output a gate scanning signal via an output port to a gate line which optionally still transmit a touch scanning signal, to switch to a high voltage level to halt the gate scanning signal while transmitting the touch scanning signal only in the gate line during a touch scan stage within the display scan stage, and to switch back to the low voltage level after the touch scan stage to output the gate scanning signal without coupling interference of the touch scanning signal. The shift register circuit is compatible for driving either 60 Hz or high-frequency (>60 Hz) Full-in-cell touch sensing display panel.

First claim

What is claimed is:

1. A shift register circuit configured to be cascaded into a gate driver on array (GOA) circuit for driving a touch sensing display panel, the shift register circuit comprising:
a first transistor having a gate coupled to an input port to receive an input signal for controlling a VDD supply voltage being passed from a source of the first transistor to a pull-up node coupled to a drain of the first transistor;
a second transistor having a gate coupled to a reset port to receive a reset signal for controlling a VSS supply voltage being passed from a source of the second transistor to the pull-up node coupled to a drain of the second transistor;
a third transistor having a gate coupled to the pull-up node and a first electrode of a first capacitor, a source connected to a first clock input port, and a drain coupled commonly to a second electrode of the first capacitor and an output port for outputting a gate scanning signal to a gate line;
a fourth transistor and a fifth transistor having a common drain connected to the output port and a common source provided with a low voltage level, the fourth transistor having a gate coupled to a switch control port, the fifth transistor having a gate connected to a pull-down node;
a sixth transistor having a drain connected to the pull-down node and a source provided with the low voltage level and a gate connected to the pull-up node;
a seventh transistor having a drain connected to the pull-up node and a source provided with the low voltage level and a gate connected to the pull-down node;
an eighth transistor having a gate connected to the pull-up node and a source connected to the switch control port;
a ninth transistor and a tenth transistor having a common gate coupled to a drain of the eighth transistor, the ninth transistor having a source connected to the switch control port and a drain connected to a source of the tenth transistor having a drain connected to the pull-up node; and
an eleventh transistor having a gate and source commonly connected to a second clock input port and a drain connected to the pull-down node and a first electrode of a second capacitor with a second electrode connected to the first clock input port;
wherein the switch control port receives a switch signal provided with a high voltage level for halting the gate scanning signal from the output port to the gate line; and
a touch scanning signal transmitted during a touch scan stage within a display scan stage is substantially free of coupling interference from any gate scanning signal.

2. The shift register circuit of claim 1 , wherein the shift register circuit is in an n-th unit of the GOA circuit comprising N numbers of units cascaded in series for respectively outputting N numbers of gate scanning signals to respective N numbers of gate lines of a display panel sequentially in an order from n=1 through n=N, wherein 1≤n≤N, wherein the input port of the n-th unit receives an input signal from an output port of the (n−1)-th unit, the reset port of the n-th unit receives a reset signal from the output port of the (n+1)-th unit of the GOA circuit, the output port of the n-th unit connects to an n-th gate line of the N numbers of gate lines, the input port of the first unit receives a start signal from a power supply and the reset port of the N-th unit receives an external RESET signal.

3. The shift register circuit of claim 2 , wherein the first clock input port and the second clock input port respectively input a first clock signal and a second clock signal, each of the first clock signal and a second clock being provided with a high voltage level and a low voltage level alternatively in a plurality of periods during the display scan stage per gate line, wherein the first clock signal and the second clock signal have an opposite phase in each of the plurality of periods.

4. The shift register circuit of claim 3 , wherein the display scan stage comprises:
a first period during which the first clock signal is provided with a low voltage level, the input signal is provided with a high voltage level from an output of the (n−1)-th unit, the switch signal is provided with a low voltage level, the pull-up node is pulled to a high voltage level and the pull-down node is pushed to a low voltage level;
a second period during which the switch signal is kept at the low voltage level, the ninth transistor and the tenth transistor is in an OFF state, the first clock signal is provided with a high voltage level, the pull-up node is bootstrapped via the first capacitor to a level higher than the high voltage level, the pull-down node remains at the low voltage level, the output port outputs the gate scanning signal at the high voltage level to the n-th gate line; and
a third period during which the reset signal is provided with a high voltage level from an output of the (n+1)-th unit to pull down the pull-up node to a low voltage level to turn off the third transistor coupled to the output port to cut off the gate scanning signal.

5. The shift register circuit of claim 4 , wherein the display scan stage further comprises:
a fourth period during which the second clock signal is provided with a high voltage level to pass the high voltage level to the pull-down node to turn on the fifth transistor for releasing noises of the output port and turn on the seventh transistor for releasing noises of the pull-up node, the pull-up node remains at the low voltage level to keep the sixth transistor in an OFF state, the output port outputs a low voltage level, wherein the fourth period is substantially overlapped in time with the third period.

6. The shift register circuit of claim 5 wherein the display scan stage further comprises:
a fifth period during which the first clock signal is provided with a high voltage level to keep the pull-down node to the high voltage level via the second capacitor and to keep the fifth transistor and the seventh transistor in an ON state for releasing noises of the output port and the pull-up node, wherein the fifth period follows the fourth period in time, the fourth period and the fifth period alternatingly repeated until the display scan stage ends.

7. The shift register circuit of claim 4 , wherein the display scan stage comprises a touch scan stage having a touch period inserted behind the first period, during which the switch signal is provided with a high voltage level to turn on the fourth transistor for releasing noises of the output port and halting the gate scanning signal from the output port to the n-th gate line to eliminate coupling interference to a touch scanning signal transmitted nearby, the first clock signal and the second clock signal are kept at a low voltage level, the pull-up node remains at the high voltage level to turn the ninth transistor and tenth transistor in an ON state to allow the high voltage level of the switch signal to continue charging the first capacitor and maintain the pull-up node at the high voltage level, wherein the touch period is at least partially overlapped in time with the second period.

8. The shift register circuit of claim 1 , wherein the input port associated with the VDD supply voltage and the reset port associated with the VSS supply voltage are interchanged.

9. The shift register circuit of claim 8 , wherein the shift register circuit is in an n-th unit of the GOA circuit comprising N numbers of units cascaded in series for respectively outputting N numbers of gate scanning signals to respective N numbers of gate lines of a display panel sequentially in an order from n=N through n=1, wherein 1≤n≤N, wherein the input port of the n-th unit receives an input signal from an output port of the (n+1)-th unit, the reset port of the n-th unit r

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Gu Honggang
• Chen Junsheng
• Shao Xianjie
• Song Jie

Classifications

• G06F3/04166

  Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving (Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184) · CPC title

• G09G3/3674 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title