Voltage drop assisted power-grid augmentation

Patent metadata

Field	Value
Publication number	US-10817645-B2
Application number	US-201916382129-A
Country	US
Kind code	B2
Filing date	Apr 11, 2019
Priority date	Apr 13, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A method for reducing voltage hot spots in a power grid for a circuit design is implemented on a computer system and includes the following steps. The computer system (e.g., an EDA tool) accesses the circuit design. The circuit design includes a power grid that distributes power throughout the circuit design. The computer system identifies spots in the power grid with excessive voltage drops. These will be referred to as hot spots. The power grid is augmented by adding local conductors at the hot spots. These local conductors provide additional electrical paths through the power grid at the hot spots. This in turn reduces the voltage drops at the hot spots.

First claim

What is claimed is:

1. A method implemented on a computer system, the computer system executing instructions to carry out a method for reducing voltage hot spots in a power grid for a circuit design, the method comprising:
accessing a circuit design, the circuit design comprising a power grid that distributes power throughout the circuit design;
identifying hot spots in the power grid with voltage drops; and
augmenting the power grid by adding local conductors at the hot spots, the local conductors providing additional electrical paths through the power grid at the hot spots, thereby reducing the voltage drops at the hot spots, wherein the power grid before augmentation comprises a plurality of distribution lines and the local conductors include straps that extend a length of some of the distribution lines.

2. The computer-implemented method of claim 1 wherein identifying hot spots is based on at least one of voltage drops for a ground net of the power grid, voltage drops for a power net of the power grid, or voltage drops across cells in the circuit design.

3. The computer-implemented method of claim 1 further comprising:
augmenting the power grid by also adding local conductors outside the hot spots, but where the power grid is more aggressively augmented at the hot spots than outside the hot spots.

4. The computer-implemented method of claim 1 wherein a design of the added local conductors is determined based in part on an effect of the local conductor on a resistance through the power grid.

5. The computer-implemented method of claim 1 wherein a design of the added local conductors is determined based in part on an effect of the local conductor on a yield of the circuit design.

6. The computer-implemented method of claim 1 wherein a design of the added local conductors is determined based in part on an effect of the local conductor on a critical area for the circuit design.

7. The computer-implemented method of claim 1 wherein a design of the added local conductors is determined based in part on an effect of the local conductor on a timing of signals through the circuit design.

8. The computer-implemented method of claim 1 further comprising:
identifying timing-critical nets, wherein a design of the added local conductors is determined based in part on a location of the timing-critical nets.

9. The computer-implemented method of claim 1 wherein the power grid before augmentation follows a regular pattern.

10. The computer-implemented method of claim 1 wherein the power grid and the local conductors are laid out on a Manhattan geometry, and the distribution lines before augmentation comprise a plurality of parallel primary distribution lines electrically connected to a plurality of secondary distribution lines that are perpendicular to the primary distribution lines.

11. The computer-implemented method of claim 10 wherein the local conductors further include shunts that electrically connect different distribution lines and/or straps.

12. The computer-implemented method of claim 11 wherein the local conductors further include shunts that electrically connect different shunts and/or straps.

13. The computer-implemented method of claim 1 wherein the circuit design is for a 16 nm or smaller technology node.

14. The computer-implemented method of claim 1 wherein the circuit design is laid out using double patterning.

15. A non-transitory computer-readable storage medium storing executable computer program instructions for reducing voltage hot spots in a power grid for a circuit design, the instructions executable by a computer system and causing the computer system to perform a method comprising:
accessing a circuit design, the circuit design comprising a power grid that distributes power throughout the circuit design;
identifying hot spots in the power grid with voltage drops; and
augmenting the power grid by adding local conductors at the hot spots, the local conductors providing additional electrical paths through the power grid at the hot spots, thereby reducing the voltage drops at the hot spots, wherein the power grid before augmentation comprises a plurality of distribution lines and the local conductors include straps that extend a length of some of the distribution lines.

16. An electronic design automation (EDA) system for reducing voltage hot spots in a power grid for a circuit design, comprising:
a data store that stores a circuit design, the circuit design comprising a power grid that distributes power throughout the circuit design; and
an EDA tool suite in communication with the data store, the EDA tool suite configured to:
identify hot spots in the power grid with voltage drops; and
augment the power grid by adding local conductors at the hot spots, the local conductors providing additional electrical paths through the power grid at the hot spots, thereby reducing the voltage drops at the hot spots, wherein the power grid before augmentation comprises a plurality of distribution lines and the local conductors include straps that extend a length of some of the distribution lines.

17. The EDA system of claim 16 wherein the EDA tool suite includes a place and route tool that identifies the hot spots in the power grid.

18. The EDA system of claim 17 wherein the EDA tool suite includes a separate EDA tool that augments the power grid by adding local conductors both at the hot spots and outside the hot spots, but that augments the power grid more aggressively at the hot spots than outside the hot spots.

19. The EDA system of claim 17 wherein the EDA tool suite includes a timing analysis tool that determines timing of signals through the circuit design, and the EDA tool suite adds local conductors based in part on an effect of the local conductor on the timing of signals through the circuit design.

Assignees

• Synopsys Inc

Inventors

• Sharma Himanshu

Classifications

• Y02E60/00

  Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title