Reducing read transactions to peripheral devices

Patent metadata

Field	Value
Publication number	US-10817448-B1
Application number	US-201916691443-A
Country	US
Kind code	B1
Filing date	Nov 21, 2019
Priority date	Mar 31, 2016
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a register or a memory location of a device. A value from the register or memory location is read. A second write transaction is sent to a block of host memory. The second write transaction includes the value and the transaction identifier.

First claim

What is claimed is:

1. A peripheral device comprising:
a bus interface;
storage circuitry including a first storage element at a first storage location and a second storage element at a second storage location; and
processing logic coupled to the storage circuitry, wherein the peripheral device is configured to:
store, in the first storage element of the peripheral device, a transaction identifier and information identifying the second storage location in response to a first write transaction received by the processing logic via the bus interface; and
transmit a second write transaction including a value stored at the second storage element and the transaction identifier to a host memory via the bus interface,
wherein the second write transaction is targeted for a read response address in the host memory.

2. The peripheral device of claim 1 , wherein the peripheral device is further configured to receive the read response address during an initialization process for the peripheral device.

3. The peripheral device of claim 1 , wherein at least one of the first storage location or the second storage location is a location in Memory-Mapped Input/Output (MMIO) memory.

4. The peripheral device of claim 1 , wherein the first storage element is either a memory element in a device memory or a register in the peripheral device.

5. The peripheral device of claim 1 , wherein the second write transaction is a Direct Memory Access (DMA) write transaction.

6. The peripheral device of claim 1 , wherein the peripheral device is further configured to receive, after expiration of a timeout period, a third write transaction including the information identifying the second storage location and a different transaction identifier.

7. The peripheral device of claim 1 , wherein the peripheral device is further configured to receive the first write transaction and transmit the second write transaction synchronously.

8. The peripheral device of claim 1 , wherein the peripheral device is further configured to receive the first write transaction and transmit the second write transaction asynchronously.

9. The peripheral device of claim 1 , wherein the information identifying the second storage location identifies the second storage location by an offset value.

10. The peripheral device of claim 1 , wherein the bus interface is configured to communicate using a Peripheral Component Interconnect (PCI) protocol.

11. A method for reading data from a peripheral device, the method comprising:
storing, in a first storage element at a first storage location of the peripheral device, a transaction identifier and information identifying a second storage element at a second storage location in response to a first write transaction received via a bus interface; and
transmitting, by the peripheral device, a second write transaction including a value stored at the second storage element and the transaction identifier to a host memory via the bus interface,
wherein the second write transaction is targeted for a read response address in the host memory.

12. The method of claim 11 , further comprising:
receiving, by the peripheral device, the read response address during an initialization process for the peripheral device.

13. The method of claim 11 , wherein at least one of the first storage location or the second storage location is a location in Memory-Mapped Input/Output (MMIO) memory.

14. The method of claim 11 , wherein the first storage element is either a memory element in a device memory or a register in the peripheral device.

15. The method of claim 11 , wherein the second write transaction is a Direct Memory Access (DMA) write transaction.

16. The method of claim 11 , further comprising:
receiving, by the peripheral device, after expiration of a timeout period, a third write transaction including the information identifying the second storage location and a different transaction identifier.

17. The method of claim 11 , further comprising:
synchronously receiving and transmitting, by the peripheral device, the first write transaction and the second write transaction, respectively.

18. The method of claim 11 , further comprising:
asynchronously receiving and transmitting, by the peripheral device, the first write transaction and the second write transaction, respectively.

19. The method of claim 11 , wherein the information identifying the second storage location identifies the second storage location by an offset value.

20. The method of claim 11 , wherein the bus interface is configured to communicate using a Peripheral Component Interconnect (PCI) protocol.

Assignees

• Amazon Tech Inc

Inventors

• Machulsky Georgy
• Bshara Nafea
• Belgazal Netanel Israel
• Bshara Said
• Schmeilin Evgeny

Classifications

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F2213/0024

  Peripheral component interconnect [PCI] · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title